On Wednesday, April 09, 2014 at 08:14:49 PM, Graham Moore wrote:
> On Wed, Apr 9, 2014 at 6:09 AM, Gerhard Sittig wrote:
> > On Wed, 2014-04-09 at 12:03 +0200, Marek Vasut wrote:
> >> On Tuesday, April 08, 2014 at 06:12:49 PM, grmo...@altera.com wrote:
> >> > From: Graham Moore
> >> >
> >> >
On Wed, Apr 9, 2014 at 6:09 AM, Gerhard Sittig wrote:
> On Wed, 2014-04-09 at 12:03 +0200, Marek Vasut wrote:
>>
>> On Tuesday, April 08, 2014 at 06:12:49 PM, grmo...@altera.com wrote:
>> > From: Graham Moore
>> >
>> > This is a slightly different version of the patch that Insop Song
>> >
On Wed, 2014-04-09 at 12:03 +0200, Marek Vasut wrote:
>
> On Tuesday, April 08, 2014 at 06:12:49 PM, grmo...@altera.com wrote:
> > From: Graham Moore
> >
> > This is a slightly different version of the patch that Insop Song
> > submitted
> >
On Wednesday, April 09, 2014 7:16 PM, Jingoo Han wrote:
> On Wednesday, April 09, 2014 7:07 PM, Marek Vasut wrote:
> > On Tuesday, April 08, 2014 at 06:12:50 PM, grmo...@altera.com wrote:
> > > From: Graham Moore
> > >
> > > Some new Micron flash chips require reading the flag
> > > status
On Wednesday, April 09, 2014 7:07 PM, Marek Vasut wrote:
> On Tuesday, April 08, 2014 at 06:12:50 PM, grmo...@altera.com wrote:
> > From: Graham Moore
> >
> > Some new Micron flash chips require reading the flag
> > status register to determine when operations have completed.
> >
> > Furthermore,
On Tuesday, April 08, 2014 at 06:12:49 PM, grmo...@altera.com wrote:
> From: Graham Moore
>
> This is a slightly different version of the patch that Insop Song
> submitted
> (http://marc.info/?i=201403012022.10111.marex%20()%20denx%20!%20de).
>
> I talked to Insop, and he agreed I should submit
On Tuesday, April 08, 2014 at 06:12:50 PM, grmo...@altera.com wrote:
> From: Graham Moore
>
> Some new Micron flash chips require reading the flag
> status register to determine when operations have completed.
>
> Furthermore, chips with multi-die stacks of the 65nm 256Mb QSPI also
> require
On Tuesday, April 08, 2014 at 06:12:50 PM, grmo...@altera.com wrote:
From: Graham Moore grmo...@altera.com
Some new Micron flash chips require reading the flag
status register to determine when operations have completed.
Furthermore, chips with multi-die stacks of the 65nm 256Mb QSPI also
On Tuesday, April 08, 2014 at 06:12:49 PM, grmo...@altera.com wrote:
From: Graham Moore grmo...@altera.com
This is a slightly different version of the patch that Insop Song
submitted
(http://marc.info/?i=201403012022.10111.marex%20()%20denx%20!%20de).
I talked to Insop, and he agreed I
On Wednesday, April 09, 2014 7:07 PM, Marek Vasut wrote:
On Tuesday, April 08, 2014 at 06:12:50 PM, grmo...@altera.com wrote:
From: Graham Moore grmo...@altera.com
Some new Micron flash chips require reading the flag
status register to determine when operations have completed.
On Wednesday, April 09, 2014 7:16 PM, Jingoo Han wrote:
On Wednesday, April 09, 2014 7:07 PM, Marek Vasut wrote:
On Tuesday, April 08, 2014 at 06:12:50 PM, grmo...@altera.com wrote:
From: Graham Moore grmo...@altera.com
Some new Micron flash chips require reading the flag
status
On Wed, 2014-04-09 at 12:03 +0200, Marek Vasut wrote:
On Tuesday, April 08, 2014 at 06:12:49 PM, grmo...@altera.com wrote:
From: Graham Moore grmo...@altera.com
This is a slightly different version of the patch that Insop Song
submitted
On Wed, Apr 9, 2014 at 6:09 AM, Gerhard Sittig g...@denx.de wrote:
On Wed, 2014-04-09 at 12:03 +0200, Marek Vasut wrote:
On Tuesday, April 08, 2014 at 06:12:49 PM, grmo...@altera.com wrote:
From: Graham Moore grmo...@altera.com
This is a slightly different version of the patch that Insop
On Wednesday, April 09, 2014 at 08:14:49 PM, Graham Moore wrote:
On Wed, Apr 9, 2014 at 6:09 AM, Gerhard Sittig g...@denx.de wrote:
On Wed, 2014-04-09 at 12:03 +0200, Marek Vasut wrote:
On Tuesday, April 08, 2014 at 06:12:49 PM, grmo...@altera.com wrote:
From: Graham Moore
On Tuesday, April 08, 2014 9:13 AM, Graham Moore
>
> From: Graham Moore
>
> Some new Micron flash chips require reading the flag status register to
> determine when operations have completed.
>
> Furthermore, chips with multi-die stacks of the 65nm 256Mb QSPI also
> require reading the
From: Graham Moore
This is a slightly different version of the patch that Insop Song
submitted (http://marc.info/?i=201403012022.10111.marex%20()%20denx%20!%20de).
I talked to Insop, and he agreed I should submit this patch as a follow-on to
his.
This patch uses a flag in the m25p_ids[] array
From: Graham Moore
Some new Micron flash chips require reading the flag
status register to determine when operations have completed.
Furthermore, chips with multi-die stacks of the 65nm 256Mb QSPI also
require reading the status register before reading the flag status register.
This patch adds
From: Graham Moore grmo...@altera.com
Some new Micron flash chips require reading the flag
status register to determine when operations have completed.
Furthermore, chips with multi-die stacks of the 65nm 256Mb QSPI also
require reading the status register before reading the flag status
From: Graham Moore grmo...@altera.com
This is a slightly different version of the patch that Insop Song
submitted (http://marc.info/?i=201403012022.10111.marex%20()%20denx%20!%20de).
I talked to Insop, and he agreed I should submit this patch as a follow-on to
his.
This patch uses a flag in
On Tuesday, April 08, 2014 9:13 AM, Graham Moore grmo...@altera.com
From: Graham Moore grmo...@altera.com
Some new Micron flash chips require reading the flag status register to
determine when operations have completed.
Furthermore, chips with multi-die stacks of the 65nm 256Mb QSPI
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