Re: [PATCH] Documentation/memory-barriers: fix a error that mistakes a CPU notion in Section Transitivity

2013-08-31 Thread Paul E. McKenney
On Sat, Aug 31, 2013 at 12:34:01PM +0800, Zhan Jianyu wrote: > Hi, Rob, thanks reviewing > and I'm sorry for my careless writing. > > I resend the revised patch below: > > --- > > The memory-barriers document may has an error in Section TRANSITIVITY. > > For transitivity, see an example

Re: [PATCH] Documentation/memory-barriers: fix a error that mistakes a CPU notion in Section Transitivity

2013-08-31 Thread Paul E. McKenney
On Sat, Aug 31, 2013 at 12:34:01PM +0800, Zhan Jianyu wrote: Hi, Rob, thanks reviewing and I'm sorry for my careless writing. I resend the revised patch below: --- The memory-barriers document may has an error in Section TRANSITIVITY. For transitivity, see an example below, given

Re: [PATCH] Documentation/memory-barriers: fix a error that mistakes a CPU notion in Section Transitivity

2013-08-30 Thread Zhan Jianyu
Hi, Rob, thanks reviewing and I'm sorry for my careless writing. I resend the revised patch below: --- The memory-barriers document may has an error in Section TRANSITIVITY. For transitivity, see an example below, given that * CPU 2's load from X follows CPU 1's store to X, * CPU 2's load

Re: [PATCH] Documentation/memory-barriers: fix a error that mistakes a CPU notion in Section Transitivity

2013-08-30 Thread Rob Landley
On 08/27/2013 05:34:22 AM, larmbr wrote: The memory-barriers document may has a error in Section TRANSITIVITY. For transitivity, see a example below, given that * CPU 2's load from X follows CPU 1's store to X, and CPU 2's load from Y preceds CPU 3's store to Y. I'd prefer somebody with a

Re: [PATCH] Documentation/memory-barriers: fix a error that mistakes a CPU notion in Section Transitivity

2013-08-30 Thread Rob Landley
On 08/27/2013 05:34:22 AM, larmbr wrote: The memory-barriers document may has a error in Section TRANSITIVITY. For transitivity, see a example below, given that * CPU 2's load from X follows CPU 1's store to X, and CPU 2's load from Y preceds CPU 3's store to Y. I'd prefer somebody with a

Re: [PATCH] Documentation/memory-barriers: fix a error that mistakes a CPU notion in Section Transitivity

2013-08-30 Thread Zhan Jianyu
Hi, Rob, thanks reviewing and I'm sorry for my careless writing. I resend the revised patch below: --- The memory-barriers document may has an error in Section TRANSITIVITY. For transitivity, see an example below, given that * CPU 2's load from X follows CPU 1's store to X, * CPU 2's load

[PATCH] Documentation/memory-barriers: fix a error that mistakes a CPU notion in Section Transitivity

2013-08-27 Thread larmbr
The memory-barriers document may has a error in Section TRANSITIVITY. For transitivity, see a example below, given that * CPU 2's load from X follows CPU 1's store to X, and CPU 2's load from Y preceds CPU 3's store to Y. CPU 1 CPU 2 CPU 3

[PATCH] Documentation/memory-barriers: fix a error that mistakes a CPU notion in Section Transitivity

2013-08-27 Thread larmbr
The memory-barriers document may has a error in Section TRANSITIVITY. For transitivity, see a example below, given that * CPU 2's load from X follows CPU 1's store to X, and CPU 2's load from Y preceds CPU 3's store to Y. CPU 1 CPU 2 CPU 3