On Sat, Aug 31, 2013 at 12:34:01PM +0800, Zhan Jianyu wrote:
> Hi, Rob, thanks reviewing
> and I'm sorry for my careless writing.
>
> I resend the revised patch below:
>
> ---
>
> The memory-barriers document may has an error in Section TRANSITIVITY.
>
> For transitivity, see an example
On Sat, Aug 31, 2013 at 12:34:01PM +0800, Zhan Jianyu wrote:
Hi, Rob, thanks reviewing
and I'm sorry for my careless writing.
I resend the revised patch below:
---
The memory-barriers document may has an error in Section TRANSITIVITY.
For transitivity, see an example below, given
Hi, Rob, thanks reviewing
and I'm sorry for my careless writing.
I resend the revised patch below:
---
The memory-barriers document may has an error in Section TRANSITIVITY.
For transitivity, see an example below, given that
* CPU 2's load from X follows CPU 1's store to X,
* CPU 2's load
On 08/27/2013 05:34:22 AM, larmbr wrote:
The memory-barriers document may has a error in Section TRANSITIVITY.
For transitivity, see a example below, given that
* CPU 2's load from X follows CPU 1's store to X, and
CPU 2's load from Y preceds CPU 3's store to Y.
I'd prefer somebody with a
On 08/27/2013 05:34:22 AM, larmbr wrote:
The memory-barriers document may has a error in Section TRANSITIVITY.
For transitivity, see a example below, given that
* CPU 2's load from X follows CPU 1's store to X, and
CPU 2's load from Y preceds CPU 3's store to Y.
I'd prefer somebody with a
Hi, Rob, thanks reviewing
and I'm sorry for my careless writing.
I resend the revised patch below:
---
The memory-barriers document may has an error in Section TRANSITIVITY.
For transitivity, see an example below, given that
* CPU 2's load from X follows CPU 1's store to X,
* CPU 2's load
The memory-barriers document may has a error in Section TRANSITIVITY.
For transitivity, see a example below, given that
* CPU 2's load from X follows CPU 1's store to X, and
CPU 2's load from Y preceds CPU 3's store to Y.
CPU 1 CPU 2 CPU 3
The memory-barriers document may has a error in Section TRANSITIVITY.
For transitivity, see a example below, given that
* CPU 2's load from X follows CPU 1's store to X, and
CPU 2's load from Y preceds CPU 3's store to Y.
CPU 1 CPU 2 CPU 3
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