On Sun, May 03, 2015 at 05:24:18PM +0100, André Hentschel wrote:
> From: André Hentschel
>
> Since commit a4780adeefd042482f624f5e0d577bf9cdcbb760 the user writeable TLS
> register on ARM is preserved per thread.
>
> This patch does it analogous to the ARM patch, but for compat mode on ARM64.
>
On Sun, May 03, 2015 at 05:24:18PM +0100, André Hentschel wrote:
From: André Hentschel n...@dawncrow.de
Since commit a4780adeefd042482f624f5e0d577bf9cdcbb760 the user writeable TLS
register on ARM is preserved per thread.
This patch does it analogous to the ARM patch, but for compat mode
On Tue, May 05, 2015 at 06:19:24PM +0100, André Hentschel wrote:
> Am 05.05.2015 um 19:15 schrieb Will Deacon:
> > On Tue, May 05, 2015 at 06:09:57PM +0100, André Hentschel wrote:
> >> Am 05.05.2015 um 12:51 schrieb Will Deacon:
> >>> On Sun, May 03, 2015 at 05:24:18PM +0100, André Hentschel
Am 05.05.2015 um 19:15 schrieb Will Deacon:
> On Tue, May 05, 2015 at 06:09:57PM +0100, André Hentschel wrote:
>> Am 05.05.2015 um 12:51 schrieb Will Deacon:
>>> On Sun, May 03, 2015 at 05:24:18PM +0100, André Hentschel wrote:
From: André Hentschel
Since commit
On Tue, May 05, 2015 at 06:09:57PM +0100, André Hentschel wrote:
> Am 05.05.2015 um 12:51 schrieb Will Deacon:
> > On Sun, May 03, 2015 at 05:24:18PM +0100, André Hentschel wrote:
> >> From: André Hentschel
> >>
> >> Since commit a4780adeefd042482f624f5e0d577bf9cdcbb760 the user writeable
> >>
Am 05.05.2015 um 12:51 schrieb Will Deacon:
> On Sun, May 03, 2015 at 05:24:18PM +0100, André Hentschel wrote:
>> From: André Hentschel
>>
>> Since commit a4780adeefd042482f624f5e0d577bf9cdcbb760 the user writeable TLS
>> register on ARM is preserved per thread.
>>
>> This patch does it analogous
On Sun, May 03, 2015 at 05:24:18PM +0100, André Hentschel wrote:
> From: André Hentschel
>
> Since commit a4780adeefd042482f624f5e0d577bf9cdcbb760 the user writeable TLS
> register on ARM is preserved per thread.
>
> This patch does it analogous to the ARM patch, but for compat mode on ARM64.
>
Am 05.05.2015 um 12:51 schrieb Will Deacon:
On Sun, May 03, 2015 at 05:24:18PM +0100, André Hentschel wrote:
From: André Hentschel n...@dawncrow.de
Since commit a4780adeefd042482f624f5e0d577bf9cdcbb760 the user writeable TLS
register on ARM is preserved per thread.
This patch does it
Am 05.05.2015 um 19:15 schrieb Will Deacon:
On Tue, May 05, 2015 at 06:09:57PM +0100, André Hentschel wrote:
Am 05.05.2015 um 12:51 schrieb Will Deacon:
On Sun, May 03, 2015 at 05:24:18PM +0100, André Hentschel wrote:
From: André Hentschel n...@dawncrow.de
Since commit
On Tue, May 05, 2015 at 06:09:57PM +0100, André Hentschel wrote:
Am 05.05.2015 um 12:51 schrieb Will Deacon:
On Sun, May 03, 2015 at 05:24:18PM +0100, André Hentschel wrote:
From: André Hentschel n...@dawncrow.de
Since commit a4780adeefd042482f624f5e0d577bf9cdcbb760 the user writeable
On Tue, May 05, 2015 at 06:19:24PM +0100, André Hentschel wrote:
Am 05.05.2015 um 19:15 schrieb Will Deacon:
On Tue, May 05, 2015 at 06:09:57PM +0100, André Hentschel wrote:
Am 05.05.2015 um 12:51 schrieb Will Deacon:
On Sun, May 03, 2015 at 05:24:18PM +0100, André Hentschel wrote:
On Sun, May 03, 2015 at 05:24:18PM +0100, André Hentschel wrote:
From: André Hentschel n...@dawncrow.de
Since commit a4780adeefd042482f624f5e0d577bf9cdcbb760 the user writeable TLS
register on ARM is preserved per thread.
This patch does it analogous to the ARM patch, but for compat mode
From: André Hentschel
Since commit a4780adeefd042482f624f5e0d577bf9cdcbb760 the user writeable TLS
register on ARM is preserved per thread.
This patch does it analogous to the ARM patch, but for compat mode on ARM64.
Signed-off-by: André Hentschel
Cc: Will Deacon
Cc: Jonathan Austin
---
From: André Hentschel n...@dawncrow.de
Since commit a4780adeefd042482f624f5e0d577bf9cdcbb760 the user writeable TLS
register on ARM is preserved per thread.
This patch does it analogous to the ARM patch, but for compat mode on ARM64.
Signed-off-by: André Hentschel n...@dawncrow.de
Cc: Will
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