On Mon, 24 Jun 2019 04:40:10 PDT (-0700), mark.rutl...@arm.com wrote:
I'm very confused by this patch. The title says arm64, yet the code is
under arch/csky/, and the code in question refers to HARTs, which IIUC
is RISC-V terminology.
On Mon, Jun 24, 2019 at 12:04:29AM +0800, guo...@kernel.org
On Mon, Jun 24, 2019 at 7:40 PM Mark Rutland wrote:
>
> I'm very confused by this patch. The title says arm64, yet the code is
> under arch/csky/, and the code in question refers to HARTs, which IIUC
> is RISC-V terminology.
This patch is used to answer Catalin's question:
> While the algorithm
I'm very confused by this patch. The title says arm64, yet the code is
under arch/csky/, and the code in question refers to HARTs, which IIUC
is RISC-V terminology.
On Mon, Jun 24, 2019 at 12:04:29AM +0800, guo...@kernel.org wrote:
> From: Guo Ren
>
> The hardware threads of one core could
From: Guo Ren
The hardware threads of one core could share the same TLB for SMT+SMP
system. Assume hardware threads number sequence like this:
| 0 1 2 3 | 4 5 6 7 | 8 9 a b | c d e f |
core1 core2 core3 core4
Current algorithm seems is correct for SMT+SMP, but it'll give some
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