To make this simpler, I think it's best to isolate the cache information
in its own patch. So I will amend this patch to include topology
information only.
On 1/31/19 3:29 PM, Bo Yan wrote:
On 1/31/19 2:25 PM, Thierry Reding wrote:
On Thu, Jan 31, 2019 at 10:35:54AM -0800, Bo Yan wrote:
On 1/31/19 2:25 PM, Thierry Reding wrote:
On Thu, Jan 31, 2019 at 10:35:54AM -0800, Bo Yan wrote:
The xavier CPU architecture includes 8 CPU cores organized in
4 clusters. Add cpu-map data for topology initialization, add
cache data for cache node creation in sysfs.
Signed-off-by: Bo Yan
On Thu, Jan 31, 2019 at 10:35:54AM -0800, Bo Yan wrote:
> The xavier CPU architecture includes 8 CPU cores organized in
> 4 clusters. Add cpu-map data for topology initialization, add
> cache data for cache node creation in sysfs.
>
> Signed-off-by: Bo Yan
> ---
>
The xavier CPU architecture includes 8 CPU cores organized in
4 clusters. Add cpu-map data for topology initialization, add
cache data for cache node creation in sysfs.
Signed-off-by: Bo Yan
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 148 +--
1 file changed, 140
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