Le jeu. 8 août 2019 à 6:08, Stephen Boyd a écrit :
Quoting Paul Cercueil (2019-08-07 16:28:10)
Le mer. 7 août 2019 à 23:33, Stephen Boyd a
écrit
:
> Quoting Paul Cercueil (2019-07-01 04:36:06)
>> The code was setting the bit 21 of the CPCCR register to use a
>> divider
>> of 2
Quoting Paul Cercueil (2019-08-07 16:28:10)
>
>
> Le mer. 7 août 2019 à 23:33, Stephen Boyd a écrit
> :
> > Quoting Paul Cercueil (2019-07-01 04:36:06)
> >> The code was setting the bit 21 of the CPCCR register to use a
> >> divider
> >> of 2 for the "pll half" clock, and clearing the bit
Le mer. 7 août 2019 à 23:33, Stephen Boyd a écrit
:
Quoting Paul Cercueil (2019-07-01 04:36:06)
The code was setting the bit 21 of the CPCCR register to use a
divider
of 2 for the "pll half" clock, and clearing the bit to use a divider
of 1.
This is the opposite of how this register
Quoting Paul Cercueil (2019-07-01 04:36:06)
> The code was setting the bit 21 of the CPCCR register to use a divider
> of 2 for the "pll half" clock, and clearing the bit to use a divider
> of 1.
>
> This is the opposite of how this register field works: a cleared bit
> means that the /2 divider
The code was setting the bit 21 of the CPCCR register to use a divider
of 2 for the "pll half" clock, and clearing the bit to use a divider
of 1.
This is the opposite of how this register field works: a cleared bit
means that the /2 divider is used, and a set bit means that the divider
is 1.
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