Re: [PATCH] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

Hello Doug, Thanks for the comments, I have based my latest patch on top of the earlier patches (clk-qcom-sdm845 branch of clk-next). On 5/1/2018 12:12 AM, Doug Anderson wrote: Hi, On Fri, Apr 27, 2018 at 1:19 AM, Taniya Das wrote: -static int gdsc_is_enabled(struct

Re: [PATCH] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

Hello Doug, Thanks for the comments, I have based my latest patch on top of the earlier patches (clk-qcom-sdm845 branch of clk-next). On 5/1/2018 12:12 AM, Doug Anderson wrote: Hi, On Fri, Apr 27, 2018 at 1:19 AM, Taniya Das wrote: -static int gdsc_is_enabled(struct gdsc *sc, unsigned

Re: [PATCH] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

Hi, On Fri, Apr 27, 2018 at 1:19 AM, Taniya Das wrote: > -static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg) > +static int gdsc_is_enabled(struct gdsc *sc, bool en) > { > + unsigned int reg; > u32 val; > int ret; > > + if (sc->flags &

Re: [PATCH] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

Hi, On Fri, Apr 27, 2018 at 1:19 AM, Taniya Das wrote: > -static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg) > +static int gdsc_is_enabled(struct gdsc *sc, bool en) > { > + unsigned int reg; > u32 val; > int ret; > > + if (sc->flags & POLL_CFG_GDSCR) > +

[PATCH] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

From: Amit Nischal The default behavior of the GDSC enable/disable sequence is to poll the status bits of either the actual GDSCR or the corresponding HW_CTRL registers. On targets which have support for a CFG_GDSCR register, the status bits might not show the correct

[PATCH] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

From: Amit Nischal The default behavior of the GDSC enable/disable sequence is to poll the status bits of either the actual GDSCR or the corresponding HW_CTRL registers. On targets which have support for a CFG_GDSCR register, the status bits might not show the correct state of the GDSC,