Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable

2017-05-04 Thread Peter De Schrijver
On Fri, Apr 21, 2017 at 07:38:48PM -0700, Stephen Boyd wrote: > On 04/20, Peter De Schrijver wrote: > > PLL SS was only controlled when setting the PLL rate, not when the PLL > > itself is enabled or disabled. This means that if the PLL rate was set > > before the PLL is enabled, SS will not be ena

Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable

2017-04-21 Thread Stephen Boyd
On 04/20, Peter De Schrijver wrote: > PLL SS was only controlled when setting the PLL rate, not when the PLL > itself is enabled or disabled. This means that if the PLL rate was set > before the PLL is enabled, SS will not be enabled, even when configured. > > Signed-off-by: Peter De Schrijver F

[PATCH] clk: tegra: fix SS control on PLL enable/disable

2017-04-20 Thread Peter De Schrijver
PLL SS was only controlled when setting the PLL rate, not when the PLL itself is enabled or disabled. This means that if the PLL rate was set before the PLL is enabled, SS will not be enabled, even when configured. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c | 44 ++

[PATCH] clk: tegra: fix SS control on PLL enable/disable

2017-04-13 Thread Peter De Schrijver
PLL SS was only controlled when setting the PLL rate, not when the PLL itself is enabled or disabled. This means that if the PLL rate was set before the PLL is enabled, SS will not be enabled, even when configured. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c | 44 ++