Re: [PATCH] crypto/nx842: Mask XERS0 bit in return value

2015-12-17 Thread Herbert Xu
On Sun, Dec 13, 2015 at 03:30:41AM -0800, Haren Myneni wrote: > > NX842 coprocessor sets 3rd bit in CR register with XER[S0] which is > nothing to do with NX request. Since this bit can be set with other > valuable return status, mast this bit. > > One of other bits (INITIATED, BUSY or REJECTED)

Re: [PATCH] crypto/nx842: Mask XERS0 bit in return value

2015-12-17 Thread Herbert Xu
On Sun, Dec 13, 2015 at 03:30:41AM -0800, Haren Myneni wrote: > > NX842 coprocessor sets 3rd bit in CR register with XER[S0] which is > nothing to do with NX request. Since this bit can be set with other > valuable return status, mast this bit. > > One of other bits (INITIATED, BUSY or REJECTED)

[PATCH] crypto/nx842: Mask XERS0 bit in return value

2015-12-13 Thread Haren Myneni
NX842 coprocessor sets 3rd bit in CR register with XER[S0] which is nothing to do with NX request. Since this bit can be set with other valuable return status, mast this bit. One of other bits (INITIATED, BUSY or REJECTED) will be returned for any given NX request. Signed-off-by: Haren Myneni

[PATCH] crypto/nx842: Mask XERS0 bit in return value

2015-12-13 Thread Haren Myneni
NX842 coprocessor sets 3rd bit in CR register with XER[S0] which is nothing to do with NX request. Since this bit can be set with other valuable return status, mast this bit. One of other bits (INITIATED, BUSY or REJECTED) will be returned for any given NX request. Signed-off-by: Haren Myneni