Re: [PATCH] iommu/amd - Set the device table entry PPR bit for IOMMU V2 devices

2017-12-12 Thread Gary R Hook
Please ignore. I've uncovered a problem and will re-submit. On 12/04/2017 01:52 PM, Gary R Hook wrote: The AMD IOMMU specification Rev 3.00 (December 2016) introduces a new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register offset 0030h (IOMMU Extended Feature Register). When

Re: [PATCH] iommu/amd - Set the device table entry PPR bit for IOMMU V2 devices

2017-12-12 Thread Gary R Hook
Please ignore. I've uncovered a problem and will re-submit. On 12/04/2017 01:52 PM, Gary R Hook wrote: The AMD IOMMU specification Rev 3.00 (December 2016) introduces a new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register offset 0030h (IOMMU Extended Feature Register). When

[PATCH] iommu/amd - Set the device table entry PPR bit for IOMMU V2 devices

2017-12-04 Thread Gary R Hook
The AMD IOMMU specification Rev 3.00 (December 2016) introduces a new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register offset 0030h (IOMMU Extended Feature Register). When EPHSup=1, the IOMMU hardware requires the PPR bit of the device table entry (DTE) to be set in order to

[PATCH] iommu/amd - Set the device table entry PPR bit for IOMMU V2 devices

2017-12-04 Thread Gary R Hook
The AMD IOMMU specification Rev 3.00 (December 2016) introduces a new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register offset 0030h (IOMMU Extended Feature Register). When EPHSup=1, the IOMMU hardware requires the PPR bit of the device table entry (DTE) to be set in order to