[...]
> > > >
> > > > From the architecture spec:
> > > >
> > > >
> > > > 11.1.3 GIC memory-mapped register access
> > > >
> > > > In any system, access to the following registers must be supported:
> > > >
> > > > [...]
> > > > * Byte accesses to:
> > > > - GICD_IPRIORITYR.
> > > >
On Tue, 30 Mar 2021 14:06:37 +0100,
Lorenzo Pieralisi wrote:
>
> On Tue, Mar 30, 2021 at 12:05:46PM +0100, Lorenzo Pieralisi wrote:
> > On Tue, Mar 30, 2021 at 11:33:13AM +0100, Marc Zyngier wrote:
> > > [+Lorenzo, +Julien on an actual email address]
> > >
> > > On Tue, 30 Mar 2021 11:06:19 +010
On Tue, Mar 30, 2021 at 12:05:46PM +0100, Lorenzo Pieralisi wrote:
> On Tue, Mar 30, 2021 at 11:33:13AM +0100, Marc Zyngier wrote:
> > [+Lorenzo, +Julien on an actual email address]
> >
> > On Tue, 30 Mar 2021 11:06:19 +0100,
> > Lecopzer Chen wrote:
> > >
> > > When pseudo-NMI enabled, register
On Tue, Mar 30, 2021 at 11:33:13AM +0100, Marc Zyngier wrote:
> [+Lorenzo, +Julien on an actual email address]
>
> On Tue, 30 Mar 2021 11:06:19 +0100,
> Lecopzer Chen wrote:
> >
> > When pseudo-NMI enabled, register_nmi() set priority of specific IRQ
> > by byte ops, and this doesn't work in GIC
[+Lorenzo, +Julien on an actual email address]
On Tue, 30 Mar 2021 11:06:19 +0100,
Lecopzer Chen wrote:
>
> When pseudo-NMI enabled, register_nmi() set priority of specific IRQ
> by byte ops, and this doesn't work in GIC-600.
>
> We have asked ARM Support [1]:
> > Please refer to following desc
When pseudo-NMI enabled, register_nmi() set priority of specific IRQ
by byte ops, and this doesn't work in GIC-600.
We have asked ARM Support [1]:
> Please refer to following description in
> "2.1.2 Distributor ACE-Lite slave interface" of GIC-600 TRM for
> the GIC600 ACE-lite slave interface supp
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