On 28 March 2017 at 11:00, Ludovic Desroches
wrote:
> The controller has different timings for MMC_TIMING_UHS_DDR50 and
> MMC_TIMING_MMC_DDR52. Configuring the controller with SDHCI_CTRL_UHS_DDR50,
> when MMC_TIMING_MMC_DDR52 timings are requested, is not correct
On 28 March 2017 at 11:00, Ludovic Desroches
wrote:
> The controller has different timings for MMC_TIMING_UHS_DDR50 and
> MMC_TIMING_MMC_DDR52. Configuring the controller with SDHCI_CTRL_UHS_DDR50,
> when MMC_TIMING_MMC_DDR52 timings are requested, is not correct and can
> lead to unexpected
The controller has different timings for MMC_TIMING_UHS_DDR50 and
MMC_TIMING_MMC_DDR52. Configuring the controller with SDHCI_CTRL_UHS_DDR50,
when MMC_TIMING_MMC_DDR52 timings are requested, is not correct and can
lead to unexpected behavior.
Signed-off-by: Ludovic Desroches
The controller has different timings for MMC_TIMING_UHS_DDR50 and
MMC_TIMING_MMC_DDR52. Configuring the controller with SDHCI_CTRL_UHS_DDR50,
when MMC_TIMING_MMC_DDR52 timings are requested, is not correct and can
lead to unexpected behavior.
Signed-off-by: Ludovic Desroches
Fixes: bb5f8ea4d514
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