Re: [PATCH] mmc: tegra: Force correct divider calculation on DDR50/52

2018-07-30 Thread Ulf Hansson
On 16 July 2018 at 16:34, Aapo Vienamo wrote: > Tegra SDHCI controllers require the SDHCI clock divider to be configured > to divide the clock by two in DDR50/52 modes. Incorrectly configured > clock divider results in corrupted data. > > Prevent the possibility of incorrectly calculating the

Re: [PATCH] mmc: tegra: Force correct divider calculation on DDR50/52

2018-07-30 Thread Ulf Hansson
On 16 July 2018 at 16:34, Aapo Vienamo wrote: > Tegra SDHCI controllers require the SDHCI clock divider to be configured > to divide the clock by two in DDR50/52 modes. Incorrectly configured > clock divider results in corrupted data. > > Prevent the possibility of incorrectly calculating the

Re: [PATCH] mmc: tegra: Force correct divider calculation on DDR50/52

2018-07-17 Thread Adrian Hunter
On 16/07/18 17:34, Aapo Vienamo wrote: > Tegra SDHCI controllers require the SDHCI clock divider to be configured > to divide the clock by two in DDR50/52 modes. Incorrectly configured > clock divider results in corrupted data. > > Prevent the possibility of incorrectly calculating the divider

Re: [PATCH] mmc: tegra: Force correct divider calculation on DDR50/52

2018-07-17 Thread Adrian Hunter
On 16/07/18 17:34, Aapo Vienamo wrote: > Tegra SDHCI controllers require the SDHCI clock divider to be configured > to divide the clock by two in DDR50/52 modes. Incorrectly configured > clock divider results in corrupted data. > > Prevent the possibility of incorrectly calculating the divider

Re: [PATCH] mmc: tegra: Force correct divider calculation on DDR50/52

2018-07-17 Thread Jon Hunter
On 17/07/18 10:08, Aapo Vienamo wrote: > On Mon, 16 Jul 2018 21:03:08 +0100 > Jon Hunter wrote: > >> On 16/07/18 15:34, Aapo Vienamo wrote: >>> Tegra SDHCI controllers require the SDHCI clock divider to be configured >>> to divide the clock by two in DDR50/52 modes. Incorrectly configured >>>

Re: [PATCH] mmc: tegra: Force correct divider calculation on DDR50/52

2018-07-17 Thread Jon Hunter
On 17/07/18 10:08, Aapo Vienamo wrote: > On Mon, 16 Jul 2018 21:03:08 +0100 > Jon Hunter wrote: > >> On 16/07/18 15:34, Aapo Vienamo wrote: >>> Tegra SDHCI controllers require the SDHCI clock divider to be configured >>> to divide the clock by two in DDR50/52 modes. Incorrectly configured >>>

Re: [PATCH] mmc: tegra: Force correct divider calculation on DDR50/52

2018-07-17 Thread Aapo Vienamo
On Mon, 16 Jul 2018 21:03:08 +0100 Jon Hunter wrote: > On 16/07/18 15:34, Aapo Vienamo wrote: > > Tegra SDHCI controllers require the SDHCI clock divider to be configured > > to divide the clock by two in DDR50/52 modes. Incorrectly configured > > clock divider results in corrupted data. > > >

Re: [PATCH] mmc: tegra: Force correct divider calculation on DDR50/52

2018-07-17 Thread Aapo Vienamo
On Mon, 16 Jul 2018 21:03:08 +0100 Jon Hunter wrote: > On 16/07/18 15:34, Aapo Vienamo wrote: > > Tegra SDHCI controllers require the SDHCI clock divider to be configured > > to divide the clock by two in DDR50/52 modes. Incorrectly configured > > clock divider results in corrupted data. > > >

Re: [PATCH] mmc: tegra: Force correct divider calculation on DDR50/52

2018-07-16 Thread Jon Hunter
On 16/07/18 15:34, Aapo Vienamo wrote: > Tegra SDHCI controllers require the SDHCI clock divider to be configured > to divide the clock by two in DDR50/52 modes. Incorrectly configured > clock divider results in corrupted data. > > Prevent the possibility of incorrectly calculating the divider

Re: [PATCH] mmc: tegra: Force correct divider calculation on DDR50/52

2018-07-16 Thread Jon Hunter
On 16/07/18 15:34, Aapo Vienamo wrote: > Tegra SDHCI controllers require the SDHCI clock divider to be configured > to divide the clock by two in DDR50/52 modes. Incorrectly configured > clock divider results in corrupted data. > > Prevent the possibility of incorrectly calculating the divider

[PATCH] mmc: tegra: Force correct divider calculation on DDR50/52

2018-07-16 Thread Aapo Vienamo
Tegra SDHCI controllers require the SDHCI clock divider to be configured to divide the clock by two in DDR50/52 modes. Incorrectly configured clock divider results in corrupted data. Prevent the possibility of incorrectly calculating the divider value due to clock rate rounding or low parent

[PATCH] mmc: tegra: Force correct divider calculation on DDR50/52

2018-07-16 Thread Aapo Vienamo
Tegra SDHCI controllers require the SDHCI clock divider to be configured to divide the clock by two in DDR50/52 modes. Incorrectly configured clock divider results in corrupted data. Prevent the possibility of incorrectly calculating the divider value due to clock rate rounding or low parent