Re: [PATCH] mmc: tegra: Mark 64 bit dma broken on Tegra186

2017-09-22 Thread Ulf Hansson
On 8 September 2017 at 21:48, Krishna Reddy wrote: > SDHCI controllers on Tegra186 support 40 bit addressing. > IOVA addresses are 48-bit wide on Tegra186. > SDHCI host common code sets dma mask as either 32-bit or 64-bit. > To avoid access issues when SMMU is enabled, disable

Re: [PATCH] mmc: tegra: Mark 64 bit dma broken on Tegra186

2017-09-22 Thread Ulf Hansson
On 8 September 2017 at 21:48, Krishna Reddy wrote: > SDHCI controllers on Tegra186 support 40 bit addressing. > IOVA addresses are 48-bit wide on Tegra186. > SDHCI host common code sets dma mask as either 32-bit or 64-bit. > To avoid access issues when SMMU is enabled, disable 64-bit dma. > >

Re: [PATCH] mmc: tegra: Mark 64 bit dma broken on Tegra186

2017-09-10 Thread Adrian Hunter
On 08/09/17 22:48, Krishna Reddy wrote: > SDHCI controllers on Tegra186 support 40 bit addressing. > IOVA addresses are 48-bit wide on Tegra186. > SDHCI host common code sets dma mask as either 32-bit or 64-bit. > To avoid access issues when SMMU is enabled, disable 64-bit dma. > > Signed-off-by:

Re: [PATCH] mmc: tegra: Mark 64 bit dma broken on Tegra186

2017-09-10 Thread Adrian Hunter
On 08/09/17 22:48, Krishna Reddy wrote: > SDHCI controllers on Tegra186 support 40 bit addressing. > IOVA addresses are 48-bit wide on Tegra186. > SDHCI host common code sets dma mask as either 32-bit or 64-bit. > To avoid access issues when SMMU is enabled, disable 64-bit dma. > > Signed-off-by:

Re: [PATCH] mmc: tegra: Mark 64 bit dma broken on Tegra186

2017-09-08 Thread Thierry Reding
On Fri, Sep 08, 2017 at 12:48:33PM -0700, Krishna Reddy wrote: > SDHCI controllers on Tegra186 support 40 bit addressing. > IOVA addresses are 48-bit wide on Tegra186. > SDHCI host common code sets dma mask as either 32-bit or 64-bit. > To avoid access issues when SMMU is enabled, disable 64-bit

Re: [PATCH] mmc: tegra: Mark 64 bit dma broken on Tegra186

2017-09-08 Thread Thierry Reding
On Fri, Sep 08, 2017 at 12:48:33PM -0700, Krishna Reddy wrote: > SDHCI controllers on Tegra186 support 40 bit addressing. > IOVA addresses are 48-bit wide on Tegra186. > SDHCI host common code sets dma mask as either 32-bit or 64-bit. > To avoid access issues when SMMU is enabled, disable 64-bit

[PATCH] mmc: tegra: Mark 64 bit dma broken on Tegra186

2017-09-08 Thread Krishna Reddy
SDHCI controllers on Tegra186 support 40 bit addressing. IOVA addresses are 48-bit wide on Tegra186. SDHCI host common code sets dma mask as either 32-bit or 64-bit. To avoid access issues when SMMU is enabled, disable 64-bit dma. Signed-off-by: Krishna Reddy ---

[PATCH] mmc: tegra: Mark 64 bit dma broken on Tegra186

2017-09-08 Thread Krishna Reddy
SDHCI controllers on Tegra186 support 40 bit addressing. IOVA addresses are 48-bit wide on Tegra186. SDHCI host common code sets dma mask as either 32-bit or 64-bit. To avoid access issues when SMMU is enabled, disable 64-bit dma. Signed-off-by: Krishna Reddy --- drivers/mmc/host/sdhci-tegra.c