Re: [PATCH] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

Hi Robert, Your patch landed in the middle of the merge window and will have to be sent again rebased on 4.19-rc1 and long with minor fix found below. Regards, Mathieu On Wed, Aug 22, 2018 at 05:03:57PM +0100, Robert Walker wrote: > This patch adds support for generating instruction samples

Re: [PATCH] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

Hi Robert, Your patch landed in the middle of the merge window and will have to be sent again rebased on 4.19-rc1 and long with minor fix found below. Regards, Mathieu On Wed, Aug 22, 2018 at 05:03:57PM +0100, Robert Walker wrote: > This patch adds support for generating instruction samples

[PATCH] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

This patch adds support for generating instruction samples from trace of AArch32 programs using the A32 and T32 instruction sets. T32 has variable 2 or 4 byte instruction size, so the conversion between addresses and instruction counts requires extra information from the trace decoder, requiring

[PATCH] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

This patch adds support for generating instruction samples from trace of AArch32 programs using the A32 and T32 instruction sets. T32 has variable 2 or 4 byte instruction size, so the conversion between addresses and instruction counts requires extra information from the trace decoder, requiring