Re: [PATCH] x86/mce/AMD: Allow any CPU to initialize smca_banks array

2017-07-16 Thread Borislav Petkov
On Thu, Jun 29, 2017 at 01:08:28PM -0500, Yazen Ghannam wrote: > From: Yazen Ghannam > > Current SMCA implementations have the same banks on each CPU with the > non-core banks only visible to a "master thread" on each Die. Practically, > this means the smca_banks array,

Re: [PATCH] x86/mce/AMD: Allow any CPU to initialize smca_banks array

2017-07-16 Thread Borislav Petkov
On Thu, Jun 29, 2017 at 01:08:28PM -0500, Yazen Ghannam wrote: > From: Yazen Ghannam > > Current SMCA implementations have the same banks on each CPU with the > non-core banks only visible to a "master thread" on each Die. Practically, > this means the smca_banks array, which describes the

Re: [PATCH] x86/mce/AMD: Allow any CPU to initialize smca_banks array

2017-06-30 Thread Jack Miller
This patch works for me, thanks! Jack On Thu, Jun 29, 2017 at 1:08 PM, Yazen Ghannam wrote: > From: Yazen Ghannam > > Current SMCA implementations have the same banks on each CPU with the > non-core banks only visible to a "master thread" on each

Re: [PATCH] x86/mce/AMD: Allow any CPU to initialize smca_banks array

2017-06-30 Thread Jack Miller
This patch works for me, thanks! Jack On Thu, Jun 29, 2017 at 1:08 PM, Yazen Ghannam wrote: > From: Yazen Ghannam > > Current SMCA implementations have the same banks on each CPU with the > non-core banks only visible to a "master thread" on each Die. Practically, > this means the smca_banks

[PATCH] x86/mce/AMD: Allow any CPU to initialize smca_banks array

2017-06-29 Thread Yazen Ghannam
From: Yazen Ghannam Current SMCA implementations have the same banks on each CPU with the non-core banks only visible to a "master thread" on each Die. Practically, this means the smca_banks array, which describes the banks, only needs to be populated once by a single

[PATCH] x86/mce/AMD: Allow any CPU to initialize smca_banks array

2017-06-29 Thread Yazen Ghannam
From: Yazen Ghannam Current SMCA implementations have the same banks on each CPU with the non-core banks only visible to a "master thread" on each Die. Practically, this means the smca_banks array, which describes the banks, only needs to be populated once by a single master thread. CPU0 seemed