On Thu, 2017-07-27 at 14:58 +0200, Joerg Roedel wrote:
> On Thu, Jul 27, 2017 at 10:01:09AM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > Mediatek's gen1 smi need the hardware larbid to identify the offset for
> > the register which controls whether enable iommu for thi
On Thu, Jul 27, 2017 at 10:01:09AM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> Mediatek's gen1 smi need the hardware larbid to identify the offset for
> the register which controls whether enable iommu for this larb.
> In the commit 3c8f4ad85c4b ("memory/mediatek: add suppo
From: Honghui Zhang
Mediatek's gen1 smi need the hardware larbid to identify the offset for
the register which controls whether enable iommu for this larb.
In the commit 3c8f4ad85c4b ("memory/mediatek: add support for mt2701"),
the larbid was used without properly initialized. This patchset fixed
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