Re: [PATCH 0/3] Get cache information from userland

2020-08-27 Thread Zong Li
On Fri, Aug 21, 2020 at 4:45 AM Palmer Dabbelt wrote: > > On Fri, 03 Jul 2020 01:57:52 PDT (-0700), zong...@sifive.com wrote: > > There are no standard CSR registers to provide cache information, the > > way for RISC-V is to get this information from DT. Currently, AT_L1I_X, > > AT_L1D_X and

Re: [PATCH 0/3] Get cache information from userland

2020-08-20 Thread Palmer Dabbelt
On Fri, 03 Jul 2020 01:57:52 PDT (-0700), zong...@sifive.com wrote: There are no standard CSR registers to provide cache information, the way for RISC-V is to get this information from DT. Currently, AT_L1I_X, AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall could use them

Re: [PATCH 0/3] Get cache information from userland

2020-07-26 Thread Zong Li
On Fri, Jul 3, 2020 at 4:57 PM Zong Li wrote: > > There are no standard CSR registers to provide cache information, the > way for RISC-V is to get this information from DT. Currently, AT_L1I_X, > AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall > could use them to get

[PATCH 0/3] Get cache information from userland

2020-07-03 Thread Zong Li
There are no standard CSR registers to provide cache information, the way for RISC-V is to get this information from DT. Currently, AT_L1I_X, AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall could use them to get information of cache through AUX vector. We exploit 'struct