Re: [PATCH 0/7] net: stmmac: Fixes and Tegra186 support

2017-02-26 Thread Thierry Reding
On Thu, Feb 23, 2017 at 12:57:05PM -0500, David Miller wrote: > > The net-next tree is closed, therefore it is not appropriate to submit > feature patches or cleanups at this time. > > Please wait for the merge window to be finished and the net-next tree > to open back up before resubmitting

Re: [PATCH 0/7] net: stmmac: Fixes and Tegra186 support

2017-02-26 Thread Thierry Reding
On Thu, Feb 23, 2017 at 12:57:05PM -0500, David Miller wrote: > > The net-next tree is closed, therefore it is not appropriate to submit > feature patches or cleanups at this time. > > Please wait for the merge window to be finished and the net-next tree > to open back up before resubmitting

Re: [PATCH 0/7] net: stmmac: Fixes and Tegra186 support

2017-02-23 Thread David Miller
The net-next tree is closed, therefore it is not appropriate to submit feature patches or cleanups at this time. Please wait for the merge window to be finished and the net-next tree to open back up before resubmitting this patch series. Thanks.

Re: [PATCH 0/7] net: stmmac: Fixes and Tegra186 support

2017-02-23 Thread David Miller
The net-next tree is closed, therefore it is not appropriate to submit feature patches or cleanups at this time. Please wait for the merge window to be finished and the net-next tree to open back up before resubmitting this patch series. Thanks.

[PATCH 0/7] net: stmmac: Fixes and Tegra186 support

2017-02-23 Thread Thierry Reding
From: Thierry Reding Hi everyone, This series of patches start with a few cleanups that I ran across while adding Tegra186 support to the stmmac driver. It then adds code for FIFO size parsing from feature registers and finally enables support for the incarnation of the

[PATCH 0/7] net: stmmac: Fixes and Tegra186 support

2017-02-23 Thread Thierry Reding
From: Thierry Reding Hi everyone, This series of patches start with a few cleanups that I ran across while adding Tegra186 support to the stmmac driver. It then adds code for FIFO size parsing from feature registers and finally enables support for the incarnation of the Synopsys DWC QOS IP