[PATCH 00/11] arm64: tegra: Add Tegra DFLL for Tegra210 Jetson TX1

This patch series implements the DFLL/CL-DVFS clock source on Tegra210 based on Tegra124 DFLL driver, Tegra210 support on Tegra124 cpufreq driver, and exposes DFLL HW as a PWM controller and provides DFLL_PWM driver to generate PWM signals to control an OpenVReg (PWM regulator) for CPU rail. This

[PATCH 00/11] arm64: tegra: Add Tegra DFLL for Tegra210 Jetson TX1

This patch series implements the DFLL/CL-DVFS clock source on Tegra210 based on Tegra124 DFLL driver, Tegra210 support on Tegra124 cpufreq driver, and exposes DFLL HW as a PWM controller and provides DFLL_PWM driver to generate PWM signals to control an OpenVReg (PWM regulator) for CPU rail. This