Re: [PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210

On Fri, Apr 22, 2016 at 06:31:03PM +0800, Penny Chiu wrote: > The DVCO present in the DFLL IP block has a separate reset line, > exposed via the CAR IP block. This reset line is asserted upon SoC > reset. Unless something (such as the DFLL driver) deasserts this > line, the DVCO will not

Re: [PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210

On Fri, Apr 22, 2016 at 06:31:03PM +0800, Penny Chiu wrote: > The DVCO present in the DFLL IP block has a separate reset line, > exposed via the CAR IP block. This reset line is asserted upon SoC > reset. Unless something (such as the DFLL driver) deasserts this > line, the DVCO will not

[PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210

The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and writes to the DFLL IP block will complete.

[PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210

The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and writes to the DFLL IP block will complete.