Formatting of Kconfig files doesn't look so pretty, so let the
Great White Handkerchief come around and clean it up.

Signed-off-by: Enrico Weigelt, metux IT consult <i...@metux.net>
---
 drivers/perf/Kconfig | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index af9bc17..468d759f 100644
--- a/drivers/perf/Kconfig
+++ b/drivers/perf/Kconfig
@@ -62,11 +62,11 @@ config ARM_DSU_PMU
          to DSU.
 
 config HISI_PMU
-       bool "HiSilicon SoC PMU"
-       depends on ARM64 && ACPI
-       help
-         Support for HiSilicon SoC uncore performance monitoring
-         unit (PMU), such as: L3C, HHA and DDRC.
+       bool "HiSilicon SoC PMU"
+       depends on ARM64 && ACPI
+       help
+         Support for HiSilicon SoC uncore performance monitoring
+         unit (PMU), such as: L3C, HHA and DDRC.
 
 config QCOM_L2_PMU
        bool "Qualcomm Technologies L2-cache PMU"
@@ -82,26 +82,26 @@ config QCOM_L3_PMU
        depends on ARCH_QCOM && ARM64 && ACPI
        select QCOM_IRQ_COMBINER
        help
-          Provides support for the L3 cache performance monitor unit (PMU)
-          in Qualcomm Technologies processors.
-          Adds the L3 cache PMU into the perf events subsystem for
-          monitoring L3 cache events.
+         Provides support for the L3 cache performance monitor unit (PMU)
+         in Qualcomm Technologies processors.
+         Adds the L3 cache PMU into the perf events subsystem for
+         monitoring L3 cache events.
 
 config THUNDERX2_PMU
        tristate "Cavium ThunderX2 SoC PMU UNCORE"
        depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA
        default m
        help
-          Provides support for ThunderX2 UNCORE events.
-          The SoC has PMU support in its L3 cache controller (L3C) and
-          in the DDR4 Memory Controller (DMC).
+         Provides support for ThunderX2 UNCORE events.
+         The SoC has PMU support in its L3 cache controller (L3C) and
+         in the DDR4 Memory Controller (DMC).
 
 config XGENE_PMU
-        depends on ARCH_XGENE
-        bool "APM X-Gene SoC PMU"
-        default n
-        help
-          Say y if you want to use APM X-Gene SoC performance monitors.
+       depends on ARCH_XGENE
+       bool "APM X-Gene SoC PMU"
+       default n
+       help
+         Say y if you want to use APM X-Gene SoC performance monitors.
 
 config ARM_SPE_PMU
        tristate "Enable support for the ARMv8.2 Statistical Profiling 
Extension"
-- 
1.9.1

Reply via email to