On Sun, Jun 12, 2016 at 08:19:47PM +0800, Dong Aisheng wrote:
> You probably may need to change the patch title after merge.
> clk: imx: fix pll clock parents
Right, thanks for the reminding.
Shawn
On Sun, Jun 12, 2016 at 08:19:47PM +0800, Dong Aisheng wrote:
> You probably may need to change the patch title after merge.
> clk: imx: fix pll clock parents
Right, thanks for the reminding.
Shawn
On Sun, Jun 12, 2016 at 07:52:04PM +0800, Dong Aisheng wrote:
> On Sun, Jun 12, 2016 at 07:43:53PM +0800, Shawn Guo wrote:
> > On Wed, Jun 08, 2016 at 10:33:36PM +0800, Dong Aisheng wrote:
> > > pllx_bypass_src mux shouldn't be the parent of pllx clock
> > > since it's only valid when when pllx
On Sun, Jun 12, 2016 at 07:52:04PM +0800, Dong Aisheng wrote:
> On Sun, Jun 12, 2016 at 07:43:53PM +0800, Shawn Guo wrote:
> > On Wed, Jun 08, 2016 at 10:33:36PM +0800, Dong Aisheng wrote:
> > > pllx_bypass_src mux shouldn't be the parent of pllx clock
> > > since it's only valid when when pllx
On Sun, Jun 12, 2016 at 07:43:53PM +0800, Shawn Guo wrote:
> On Wed, Jun 08, 2016 at 10:33:36PM +0800, Dong Aisheng wrote:
> > pllx_bypass_src mux shouldn't be the parent of pllx clock
> > since it's only valid when when pllx BYPASS bit is set.
> > Thus it is actually one parent of pllx_bypass
On Sun, Jun 12, 2016 at 07:43:53PM +0800, Shawn Guo wrote:
> On Wed, Jun 08, 2016 at 10:33:36PM +0800, Dong Aisheng wrote:
> > pllx_bypass_src mux shouldn't be the parent of pllx clock
> > since it's only valid when when pllx BYPASS bit is set.
> > Thus it is actually one parent of pllx_bypass
On Wed, Jun 08, 2016 at 10:33:36PM +0800, Dong Aisheng wrote:
> pllx_bypass_src mux shouldn't be the parent of pllx clock
> since it's only valid when when pllx BYPASS bit is set.
> Thus it is actually one parent of pllx_bypass only.
>
> Instead, pllx parent should be fixed to osc according to
>
On Wed, Jun 08, 2016 at 10:33:36PM +0800, Dong Aisheng wrote:
> pllx_bypass_src mux shouldn't be the parent of pllx clock
> since it's only valid when when pllx BYPASS bit is set.
> Thus it is actually one parent of pllx_bypass only.
>
> Instead, pllx parent should be fixed to osc according to
>
pllx_bypass_src mux shouldn't be the parent of pllx clock
since it's only valid when when pllx BYPASS bit is set.
Thus it is actually one parent of pllx_bypass only.
Instead, pllx parent should be fixed to osc according to
reference manual.
Other plls have the same issue.
e.g. before fix, the
pllx_bypass_src mux shouldn't be the parent of pllx clock
since it's only valid when when pllx BYPASS bit is set.
Thus it is actually one parent of pllx_bypass only.
Instead, pllx parent should be fixed to osc according to
reference manual.
Other plls have the same issue.
e.g. before fix, the
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