Re: [PATCH 09/15] riscv: implement remote sfence.i natively for M-mode

On Tue, 2019-08-13 at 17:47 +0200, Christoph Hellwig wrote: > The RISC-V ISA only supports flushing the instruction cache for the > local > CPU core. For normal S-mode Linux remote flushing is offloaded to > machine mode using ecalls, but for M-mode Linux we'll have to do it > ourselves. Use the

[PATCH 09/15] riscv: implement remote sfence.i natively for M-mode

The RISC-V ISA only supports flushing the instruction cache for the local CPU core. For normal S-mode Linux remote flushing is offloaded to machine mode using ecalls, but for M-mode Linux we'll have to do it ourselves. Use the same implementation as all the existing open source SBI