Hello Kukjin,
On 01/23/2015 07:51 AM, Kukjin Kim wrote:
>> >>
>> >> Acked-by: Sylwester Nawrocki
>> >
>> > Acked-by: Michael Turquette
>> >
>>
>> Thanks a lot Sylwester and Mike for your acks.
>>
>> Kukjin, could you please pick $subject and "Patch 2/2 ARM: dts: Add DISP1
>> power domain for
Hello Kukjin,
On 01/23/2015 07:51 AM, Kukjin Kim wrote:
Acked-by: Sylwester Nawrocki s.nawro...@samsung.com
Acked-by: Michael Turquette mturque...@linaro.org
Thanks a lot Sylwester and Mike for your acks.
Kukjin, could you please pick $subject and Patch 2/2 ARM: dts: Add DISP1
Javier Martinez Canillas wrote:
>
> Hello,
>
Hi,
> On 01/20/2015 06:54 PM, Mike Turquette wrote:
> > Quoting Sylwester Nawrocki (2015-01-20 06:04:00)
> >> Hi,
> >>
> >> On 20/01/15 11:35, Javier Martinez Canillas wrote:
> >> > When a power domain is powered off on Exynos5420 SoC, the input
Javier Martinez Canillas wrote:
Hello,
Hi,
On 01/20/2015 06:54 PM, Mike Turquette wrote:
Quoting Sylwester Nawrocki (2015-01-20 06:04:00)
Hi,
On 20/01/15 11:35, Javier Martinez Canillas wrote:
When a power domain is powered off on Exynos5420 SoC, the input clocks of
the
Hello,
On 01/20/2015 06:54 PM, Mike Turquette wrote:
> Quoting Sylwester Nawrocki (2015-01-20 06:04:00)
>> Hi,
>>
>> On 20/01/15 11:35, Javier Martinez Canillas wrote:
>> > When a power domain is powered off on Exynos5420 SoC, the input clocks of
>> > the devices attached to this power domain
Hello,
On 01/20/2015 06:54 PM, Mike Turquette wrote:
Quoting Sylwester Nawrocki (2015-01-20 06:04:00)
Hi,
On 20/01/15 11:35, Javier Martinez Canillas wrote:
When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented
Quoting Sylwester Nawrocki (2015-01-20 06:04:00)
> Hi,
>
> On 20/01/15 11:35, Javier Martinez Canillas wrote:
> > When a power domain is powered off on Exynos5420 SoC, the input clocks of
> > the devices attached to this power domain are re-parented to oscclk and
> > restored to the original
Hi,
On 20/01/15 11:35, Javier Martinez Canillas wrote:
> When a power domain is powered off on Exynos5420 SoC, the input clocks of
> the devices attached to this power domain are re-parented to oscclk and
> restored to the original parent after powering on the power domain.
>
> So a reference to
When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.
So a reference to the input and parent clocks for the devices attached to
a power
When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.
So a reference to the input and parent clocks for the devices attached to
a power
Hi,
On 20/01/15 11:35, Javier Martinez Canillas wrote:
When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.
So a reference to the
Quoting Sylwester Nawrocki (2015-01-20 06:04:00)
Hi,
On 20/01/15 11:35, Javier Martinez Canillas wrote:
When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after
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