Re: [PATCH 1/2] mips: Add strong UC ordering config

2020-09-25 Thread Serge Semin
On Fri, Sep 25, 2020 at 11:54:20AM +0800, Jiaxun Yang wrote: > > > 在 2020/9/20 19:00, Serge Semin 写道: > > In accordance with [1, 2] memory transactions using CCA=2 (Uncached > > Cacheability and Coherency Attribute) are always strongly ordered. This > > means the younger memory accesses using

Re: [PATCH 1/2] mips: Add strong UC ordering config

2020-09-24 Thread Jiaxun Yang
在 2020/9/20 19:00, Serge Semin 写道: In accordance with [1, 2] memory transactions using CCA=2 (Uncached Cacheability and Coherency Attribute) are always strongly ordered. This means the younger memory accesses using CCA=2 are never allowed to be executed before older memory accesses using

[PATCH 1/2] mips: Add strong UC ordering config

2020-09-20 Thread Serge Semin
In accordance with [1, 2] memory transactions using CCA=2 (Uncached Cacheability and Coherency Attribute) are always strongly ordered. This means the younger memory accesses using CCA=2 are never allowed to be executed before older memory accesses using CCA=2 (no bypassing is allowed), and Loads