Re: [PATCH 1/2] perf, x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X

2013-08-19 Thread Peter Zijlstra
On Mon, Aug 19, 2013 at 04:24:56PM +0200, Stephane Eranian wrote: > On Thu, Jul 18, 2013 at 11:02 AM, Yan, Zheng wrote: > > From: "Yan, Zheng" > > > > Silvermont (22nm Atom) has two offcore response configuration MSRs, > > unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7. >

Re: [PATCH 1/2] perf, x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X

2013-08-19 Thread Stephane Eranian
On Thu, Jul 18, 2013 at 11:02 AM, Yan, Zheng wrote: > From: "Yan, Zheng" > > Silvermont (22nm Atom) has two offcore response configuration MSRs, > unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7. > To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to >

Re: [PATCH 1/2] perf, x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X

2013-08-19 Thread Stephane Eranian
On Thu, Jul 18, 2013 at 11:02 AM, Yan, Zheng zheng.z@intel.com wrote: From: Yan, Zheng zheng.z@intel.com Silvermont (22nm Atom) has two offcore response configuration MSRs, unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7. To avoid complicating intel_fixup_er(),

Re: [PATCH 1/2] perf, x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X

2013-08-19 Thread Peter Zijlstra
On Mon, Aug 19, 2013 at 04:24:56PM +0200, Stephane Eranian wrote: On Thu, Jul 18, 2013 at 11:02 AM, Yan, Zheng zheng.z@intel.com wrote: From: Yan, Zheng zheng.z@intel.com Silvermont (22nm Atom) has two offcore response configuration MSRs, unlike other Intel CPU, its event code for

Re: [PATCH 1/2] perf, x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X

2013-08-18 Thread Yan, Zheng
ping On 07/18/2013 05:02 PM, Yan, Zheng wrote: > From: "Yan, Zheng" > > Silvermont (22nm Atom) has two offcore response configuration MSRs, > unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7. > To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to > define

Re: [PATCH 1/2] perf, x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X

2013-08-18 Thread Yan, Zheng
ping On 07/18/2013 05:02 PM, Yan, Zheng wrote: From: Yan, Zheng zheng.z@intel.com Silvermont (22nm Atom) has two offcore response configuration MSRs, unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7. To avoid complicating intel_fixup_er(), use

[PATCH 1/2] perf, x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X

2013-07-18 Thread Yan, Zheng
From: "Yan, Zheng" Silvermont (22nm Atom) has two offcore response configuration MSRs, unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7. To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X. So intel_fixup_er() can find the event

[PATCH 1/2] perf, x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X

2013-07-18 Thread Yan, Zheng
From: Yan, Zheng zheng.z@intel.com Silvermont (22nm Atom) has two offcore response configuration MSRs, unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7. To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X. So intel_fixup_er()