On Mon, Aug 19, 2013 at 04:24:56PM +0200, Stephane Eranian wrote:
> On Thu, Jul 18, 2013 at 11:02 AM, Yan, Zheng wrote:
> > From: "Yan, Zheng"
> >
> > Silvermont (22nm Atom) has two offcore response configuration MSRs,
> > unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7.
>
On Thu, Jul 18, 2013 at 11:02 AM, Yan, Zheng wrote:
> From: "Yan, Zheng"
>
> Silvermont (22nm Atom) has two offcore response configuration MSRs,
> unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7.
> To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to
>
On Thu, Jul 18, 2013 at 11:02 AM, Yan, Zheng zheng.z@intel.com wrote:
From: Yan, Zheng zheng.z@intel.com
Silvermont (22nm Atom) has two offcore response configuration MSRs,
unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7.
To avoid complicating intel_fixup_er(),
On Mon, Aug 19, 2013 at 04:24:56PM +0200, Stephane Eranian wrote:
On Thu, Jul 18, 2013 at 11:02 AM, Yan, Zheng zheng.z@intel.com wrote:
From: Yan, Zheng zheng.z@intel.com
Silvermont (22nm Atom) has two offcore response configuration MSRs,
unlike other Intel CPU, its event code for
ping
On 07/18/2013 05:02 PM, Yan, Zheng wrote:
> From: "Yan, Zheng"
>
> Silvermont (22nm Atom) has two offcore response configuration MSRs,
> unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7.
> To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to
> define
ping
On 07/18/2013 05:02 PM, Yan, Zheng wrote:
From: Yan, Zheng zheng.z@intel.com
Silvermont (22nm Atom) has two offcore response configuration MSRs,
unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7.
To avoid complicating intel_fixup_er(), use
From: "Yan, Zheng"
Silvermont (22nm Atom) has two offcore response configuration MSRs,
unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7.
To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to
define MSR_OFFCORE_RSP_X. So intel_fixup_er() can find the event
From: Yan, Zheng zheng.z@intel.com
Silvermont (22nm Atom) has two offcore response configuration MSRs,
unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7.
To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to
define MSR_OFFCORE_RSP_X. So intel_fixup_er()
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