ail.com; linux-kernel@vger.kernel.org; linux-arm-
>ker...@lists.infradead.org; devicet...@vger.kernel.org; Ajay Yugalkishore
>Pandey
>
>Subject: Re: [PATCH 1/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core
>
>
>
>On 9/25/2018 12:57 PM, Anurag Kumar Vulisha wrote:
>&
ail.com; linux-kernel@vger.kernel.org; linux-arm-
>ker...@lists.infradead.org; devicet...@vger.kernel.org; Ajay Yugalkishore
>Pandey
>
>Subject: Re: [PATCH 1/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core
>
>
>
>On 9/25/2018 12:57 PM, Anurag Kumar Vulisha wrote:
>&
Kumar Vulisha ; Michal Simek
; robh...@kernel.org; mark.rutl...@arm.com;
vivek.gau...@codeaurora.org
Cc: v.anuragku...@gmail.com; linux-kernel@vger.kernel.org; linux-arm-
ker...@lists.infradead.org; devicet...@vger.kernel.org
Subject: Re: [PATCH 1/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy
Kumar Vulisha ; Michal Simek
; robh...@kernel.org; mark.rutl...@arm.com;
vivek.gau...@codeaurora.org
Cc: v.anuragku...@gmail.com; linux-kernel@vger.kernel.org; linux-arm-
ker...@lists.infradead.org; devicet...@vger.kernel.org
Subject: Re: [PATCH 1/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy
h...@kernel.org; mark.rutl...@arm.com;
>vivek.gau...@codeaurora.org
>Cc: v.anuragku...@gmail.com; linux-kernel@vger.kernel.org; linux-arm-
>ker...@lists.infradead.org; devicet...@vger.kernel.org
>Subject: Re: [PATCH 1/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core
>
>Hi,
>
h...@kernel.org; mark.rutl...@arm.com;
>vivek.gau...@codeaurora.org
>Cc: v.anuragku...@gmail.com; linux-kernel@vger.kernel.org; linux-arm-
>ker...@lists.infradead.org; devicet...@vger.kernel.org
>Subject: Re: [PATCH 1/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core
>
>Hi,
>
Hi,
On Wednesday 29 August 2018 07:37 PM, Anurag Kumar Vulisha wrote:
> ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed
> peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can
> rely on any of the four GT lanes for PHY layer. This patch adds driver
>
Hi,
On Wednesday 29 August 2018 07:37 PM, Anurag Kumar Vulisha wrote:
> ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed
> peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can
> rely on any of the four GT lanes for PHY layer. This patch adds driver
>
ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed
peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can
rely on any of the four GT lanes for PHY layer. This patch adds driver
for that ZynqMP GT core.
Signed-off-by: Anurag Kumar Vulisha
---
ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed
peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can
rely on any of the four GT lanes for PHY layer. This patch adds driver
for that ZynqMP GT core.
Signed-off-by: Anurag Kumar Vulisha
---
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