Re: [PATCH 1/3] irqchip/irq-sifive-plic: Fixup wrong size of xxx_PER_HART and reg base

2020-10-26 Thread Guo Ren
Hi Anup, On Sun, Oct 25, 2020 at 5:18 PM Anup Patel wrote: > > On Sat, Oct 24, 2020 at 8:40 AM Guo Ren wrote: > > > > On Fri, Oct 23, 2020 at 8:31 PM Anup Patel wrote: > > > > > > On Fri, Oct 23, 2020 at 3:48 PM wrote: > > > > > > > > From: Guo Ren > > > > > > > > ENABLE and CONTEXT

Re: [PATCH 1/3] irqchip/irq-sifive-plic: Fixup wrong size of xxx_PER_HART and reg base

2020-10-25 Thread Anup Patel
On Sat, Oct 24, 2020 at 8:40 AM Guo Ren wrote: > > On Fri, Oct 23, 2020 at 8:31 PM Anup Patel wrote: > > > > On Fri, Oct 23, 2020 at 3:48 PM wrote: > > > > > > From: Guo Ren > > > > > > ENABLE and CONTEXT registers contain M & S status for per-hart, so > > > ref to the specification the

Re: [PATCH 1/3] irqchip/irq-sifive-plic: Fixup wrong size of xxx_PER_HART and reg base

2020-10-23 Thread Guo Ren
On Fri, Oct 23, 2020 at 8:31 PM Anup Patel wrote: > > On Fri, Oct 23, 2020 at 3:48 PM wrote: > > > > From: Guo Ren > > > > ENABLE and CONTEXT registers contain M & S status for per-hart, so > > ref to the specification the correct definition is double to the > > current value. > > > > The value

Re: [PATCH 1/3] irqchip/irq-sifive-plic: Fixup wrong size of xxx_PER_HART and reg base

2020-10-23 Thread Anup Patel
On Fri, Oct 23, 2020 at 3:48 PM wrote: > > From: Guo Ren > > ENABLE and CONTEXT registers contain M & S status for per-hart, so > ref to the specification the correct definition is double to the > current value. > > The value of hart_base and enable_base should be calculated by real > physical

[PATCH 1/3] irqchip/irq-sifive-plic: Fixup wrong size of xxx_PER_HART and reg base

2020-10-23 Thread guoren
From: Guo Ren ENABLE and CONTEXT registers contain M & S status for per-hart, so ref to the specification the correct definition is double to the current value. The value of hart_base and enable_base should be calculated by real physical hartid not software id. Sometimes the CPU node's from