Hi Anup,
On Sun, Oct 25, 2020 at 5:18 PM Anup Patel wrote:
>
> On Sat, Oct 24, 2020 at 8:40 AM Guo Ren wrote:
> >
> > On Fri, Oct 23, 2020 at 8:31 PM Anup Patel wrote:
> > >
> > > On Fri, Oct 23, 2020 at 3:48 PM wrote:
> > > >
> > > > From: Guo Ren
> > > >
> > > > ENABLE and CONTEXT
On Sat, Oct 24, 2020 at 8:40 AM Guo Ren wrote:
>
> On Fri, Oct 23, 2020 at 8:31 PM Anup Patel wrote:
> >
> > On Fri, Oct 23, 2020 at 3:48 PM wrote:
> > >
> > > From: Guo Ren
> > >
> > > ENABLE and CONTEXT registers contain M & S status for per-hart, so
> > > ref to the specification the
On Fri, Oct 23, 2020 at 8:31 PM Anup Patel wrote:
>
> On Fri, Oct 23, 2020 at 3:48 PM wrote:
> >
> > From: Guo Ren
> >
> > ENABLE and CONTEXT registers contain M & S status for per-hart, so
> > ref to the specification the correct definition is double to the
> > current value.
> >
> > The value
On Fri, Oct 23, 2020 at 3:48 PM wrote:
>
> From: Guo Ren
>
> ENABLE and CONTEXT registers contain M & S status for per-hart, so
> ref to the specification the correct definition is double to the
> current value.
>
> The value of hart_base and enable_base should be calculated by real
> physical
From: Guo Ren
ENABLE and CONTEXT registers contain M & S status for per-hart, so
ref to the specification the correct definition is double to the
current value.
The value of hart_base and enable_base should be calculated by real
physical hartid not software id. Sometimes the CPU node's
from
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