Il 19/01/21 16:07, Vinod Koul ha scritto:
Patch 2 had two blank lines getting inserted, I have fixed that up while
applying.. so:
Applied all, thanks
Thank you!
On 14-01-21, 18:47, AngeloGioacchino Del Regno wrote:
> The TCSR's PHY_CLK_SCHEME register is not available on all SoC
> models, but some may still use a differential reference clock.
>
> In preparation for these SoCs, add a se_clk_scheme_default
> configuration entry and declare it to true for al
Il 14/01/21 18:52, Bjorn Andersson ha scritto:
On Thu 14 Jan 11:47 CST 2021, AngeloGioacchino Del Regno wrote:
The TCSR's PHY_CLK_SCHEME register is not available on all SoC
models, but some may still use a differential reference clock.
In preparation for these SoCs, add a se_clk_scheme_defaul
On Thu 14 Jan 11:47 CST 2021, AngeloGioacchino Del Regno wrote:
> The TCSR's PHY_CLK_SCHEME register is not available on all SoC
> models, but some may still use a differential reference clock.
>
> In preparation for these SoCs, add a se_clk_scheme_default
> configuration entry and declare it to
The TCSR's PHY_CLK_SCHEME register is not available on all SoC
models, but some may still use a differential reference clock.
In preparation for these SoCs, add a se_clk_scheme_default
configuration entry and declare it to true for all currently
supported SoCs (retaining the previous defaults.
Th
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