Re: [PATCH 1/5] KVM: nVMX: Make nested control MSRs per-cpu.

2015-01-21 Thread Paolo Bonzini
On 21/01/2015 10:23, Wincy Van wrote: > Yes, moving that msrs looks a bit ugly, but the irqchip_in_kernel is > per-VM, not a global > setting, there would be different settings of kernel_irqchip between VMs. > If we use irqchip_in_kernel to check it and set different value of the > ctl msrs, I

Re: [PATCH 1/5] KVM: nVMX: Make nested control MSRs per-cpu.

2015-01-21 Thread Wincy Van
On Wed, Jan 21, 2015 at 4:18 PM, Zhang, Yang Z wrote: > Wincy Van wrote on 2015-01-16: >> To enable nested apicv support, we need per-cpu vmx control MSRs: >> 1. If in-kernel irqchip is enabled, we can enable nested >> posted interrupt, we should set posted intr bit in the >>

RE: [PATCH 1/5] KVM: nVMX: Make nested control MSRs per-cpu.

2015-01-21 Thread Zhang, Yang Z
Wincy Van wrote on 2015-01-16: > To enable nested apicv support, we need per-cpu vmx control MSRs: > 1. If in-kernel irqchip is enabled, we can enable nested > posted interrupt, we should set posted intr bit in the > nested_vmx_pinbased_ctls_high. 2. If in-kernel irqchip is disabled, >

Re: [PATCH 1/5] KVM: nVMX: Make nested control MSRs per-cpu.

2015-01-21 Thread Paolo Bonzini
On 21/01/2015 10:23, Wincy Van wrote: Yes, moving that msrs looks a bit ugly, but the irqchip_in_kernel is per-VM, not a global setting, there would be different settings of kernel_irqchip between VMs. If we use irqchip_in_kernel to check it and set different value of the ctl msrs, I think

RE: [PATCH 1/5] KVM: nVMX: Make nested control MSRs per-cpu.

2015-01-21 Thread Zhang, Yang Z
Wincy Van wrote on 2015-01-16: To enable nested apicv support, we need per-cpu vmx control MSRs: 1. If in-kernel irqchip is enabled, we can enable nested posted interrupt, we should set posted intr bit in the nested_vmx_pinbased_ctls_high. 2. If in-kernel irqchip is disabled,

Re: [PATCH 1/5] KVM: nVMX: Make nested control MSRs per-cpu.

2015-01-21 Thread Wincy Van
On Wed, Jan 21, 2015 at 4:18 PM, Zhang, Yang Z yang.z.zh...@intel.com wrote: Wincy Van wrote on 2015-01-16: To enable nested apicv support, we need per-cpu vmx control MSRs: 1. If in-kernel irqchip is enabled, we can enable nested posted interrupt, we should set posted intr bit in the

[PATCH 1/5] KVM: nVMX: Make nested control MSRs per-cpu.

2015-01-15 Thread Wincy Van
To enable nested apicv support, we need per-cpu vmx control MSRs: 1. If in-kernel irqchip is enabled, we can enable nested posted interrupt, we should set posted intr bit in the nested_vmx_pinbased_ctls_high. 2. If in-kernel irqchip is disabled, we can not enable nested posted

[PATCH 1/5] KVM: nVMX: Make nested control MSRs per-cpu.

2015-01-15 Thread Wincy Van
To enable nested apicv support, we need per-cpu vmx control MSRs: 1. If in-kernel irqchip is enabled, we can enable nested posted interrupt, we should set posted intr bit in the nested_vmx_pinbased_ctls_high. 2. If in-kernel irqchip is disabled, we can not enable nested posted