On 21/01/2015 10:23, Wincy Van wrote:
> Yes, moving that msrs looks a bit ugly, but the irqchip_in_kernel is
> per-VM, not a global
> setting, there would be different settings of kernel_irqchip between VMs.
> If we use irqchip_in_kernel to check it and set different value of the
> ctl msrs, I
On Wed, Jan 21, 2015 at 4:18 PM, Zhang, Yang Z wrote:
> Wincy Van wrote on 2015-01-16:
>> To enable nested apicv support, we need per-cpu vmx control MSRs:
>> 1. If in-kernel irqchip is enabled, we can enable nested
>> posted interrupt, we should set posted intr bit in the
>>
Wincy Van wrote on 2015-01-16:
> To enable nested apicv support, we need per-cpu vmx control MSRs:
> 1. If in-kernel irqchip is enabled, we can enable nested
> posted interrupt, we should set posted intr bit in the
> nested_vmx_pinbased_ctls_high. 2. If in-kernel irqchip is disabled,
>
On 21/01/2015 10:23, Wincy Van wrote:
Yes, moving that msrs looks a bit ugly, but the irqchip_in_kernel is
per-VM, not a global
setting, there would be different settings of kernel_irqchip between VMs.
If we use irqchip_in_kernel to check it and set different value of the
ctl msrs, I think
Wincy Van wrote on 2015-01-16:
To enable nested apicv support, we need per-cpu vmx control MSRs:
1. If in-kernel irqchip is enabled, we can enable nested
posted interrupt, we should set posted intr bit in the
nested_vmx_pinbased_ctls_high. 2. If in-kernel irqchip is disabled,
On Wed, Jan 21, 2015 at 4:18 PM, Zhang, Yang Z yang.z.zh...@intel.com wrote:
Wincy Van wrote on 2015-01-16:
To enable nested apicv support, we need per-cpu vmx control MSRs:
1. If in-kernel irqchip is enabled, we can enable nested
posted interrupt, we should set posted intr bit in the
To enable nested apicv support, we need per-cpu vmx
control MSRs:
1. If in-kernel irqchip is enabled, we can enable nested
posted interrupt, we should set posted intr bit in
the nested_vmx_pinbased_ctls_high.
2. If in-kernel irqchip is disabled, we can not enable
nested posted
To enable nested apicv support, we need per-cpu vmx
control MSRs:
1. If in-kernel irqchip is enabled, we can enable nested
posted interrupt, we should set posted intr bit in
the nested_vmx_pinbased_ctls_high.
2. If in-kernel irqchip is disabled, we can not enable
nested posted
8 matches
Mail list logo