Re: [linux-sunxi] [PATCH 1/5] clk: sunxi-ng: prevent NKMP clocks from temporarily get higher freq

Hi Icenowy, I already tried this approach to changing CPUX_PLL and it didn't work well. I've written a test program for CPUS (additional RISC-V processor on H3 SoC) for testing various NKMP clock change algorithms, by randomly changing the PLL frequency. Everything except simply not using

Re: [linux-sunxi] [PATCH 1/5] clk: sunxi-ng: prevent NKMP clocks from temporarily get higher freq

Hi Icenowy, I already tried this approach to changing CPUX_PLL and it didn't work well. I've written a test program for CPUS (additional RISC-V processor on H3 SoC) for testing various NKMP clock change algorithms, by randomly changing the PLL frequency. Everything except simply not using

[PATCH 1/5] clk: sunxi-ng: prevent NKMP clocks from temporarily get higher freq

It seems that on newer SoCs (already observed on A33, H3), when setting all NKMP factors at the same time, the multiplier get applied first, then the divider get applied. In some situations (e.g. the multiplier increased but the divider decreased), this will make the clock frequency temporarily

[PATCH 1/5] clk: sunxi-ng: prevent NKMP clocks from temporarily get higher freq

It seems that on newer SoCs (already observed on A33, H3), when setting all NKMP factors at the same time, the multiplier get applied first, then the divider get applied. In some situations (e.g. the multiplier increased but the divider decreased), this will make the clock frequency temporarily