Boris Brezillon writes:
> On Thu, 29 Oct 2015 18:23:47 +0100
> Marek Vasut wrote:
> Except it's now how devices supporting 16 bits data bus are supposed to
> work, which means your NAND controller will probably not be able to
> send the command/address value on the higher 8 bits...
Correct.
>>
On Thu, 29 Oct 2015 18:23:47 +0100
Marek Vasut wrote:
> On Thursday, October 29, 2015 at 08:24:48 AM, Boris Brezillon wrote:
> > Hi Robert,
>
> Hi!
>
> > On Thu, 29 Oct 2015 07:32:33 +0100
> >
> > Robert Jarzmik wrote:
> > > Marek Vasut writes:
> > > >> Isn't there the case of a single NAND
On Thursday, October 29, 2015 at 08:24:48 AM, Boris Brezillon wrote:
> Hi Robert,
Hi!
> On Thu, 29 Oct 2015 07:32:33 +0100
>
> Robert Jarzmik wrote:
> > Marek Vasut writes:
> > >> Isn't there the case of a single NAND controller with 2 identical
> > >> chips, each a 8 bit NAND chip, and the
Hi Robert,
On Thu, 29 Oct 2015 07:32:33 +0100
Robert Jarzmik wrote:
> Marek Vasut writes:
>
> >> Isn't there the case of a single NAND controller with 2 identical chips,
> >> each a 8 bit NAND chip, and the controller aggregating them to offer the
> >> OS a single 16-bit NAND chip ?
Marek Vasut writes:
>> Isn't there the case of a single NAND controller with 2 identical chips,
>> each a 8 bit NAND chip, and the controller aggregating them to offer the
>> OS a single 16-bit NAND chip ?
>
> Is that using 1 or 2 physical chipselect lines on the CPU (controller) ?
I think it's
On Thursday, October 29, 2015 at 08:24:48 AM, Boris Brezillon wrote:
> Hi Robert,
Hi!
> On Thu, 29 Oct 2015 07:32:33 +0100
>
> Robert Jarzmik wrote:
> > Marek Vasut writes:
> > >> Isn't there the case of a single NAND controller with 2 identical
> > >>
On Thu, 29 Oct 2015 18:23:47 +0100
Marek Vasut wrote:
> On Thursday, October 29, 2015 at 08:24:48 AM, Boris Brezillon wrote:
> > Hi Robert,
>
> Hi!
>
> > On Thu, 29 Oct 2015 07:32:33 +0100
> >
> > Robert Jarzmik wrote:
> > > Marek Vasut
Boris Brezillon writes:
> On Thu, 29 Oct 2015 18:23:47 +0100
> Marek Vasut wrote:
> Except it's now how devices supporting 16 bits data bus are supposed to
> work, which means your NAND controller will probably not be able to
> send the
Hi Robert,
On Thu, 29 Oct 2015 07:32:33 +0100
Robert Jarzmik wrote:
> Marek Vasut writes:
>
> >> Isn't there the case of a single NAND controller with 2 identical chips,
> >> each a 8 bit NAND chip, and the controller aggregating them to offer the
> >>
Marek Vasut writes:
>> Isn't there the case of a single NAND controller with 2 identical chips,
>> each a 8 bit NAND chip, and the controller aggregating them to offer the
>> OS a single 16-bit NAND chip ?
>
> Is that using 1 or 2 physical chipselect lines on the CPU (controller)
On Wednesday, October 28, 2015 at 09:55:24 PM, Robert Jarzmik wrote:
> Brian Norris writes:
> >> > Do some sorts of chipselects come into play here ? Ie. you can have
> >> > one master with multiple NAND chips connected to it.
> >>
> >> Most NAND controllers support interacting with several
Brian Norris writes:
>> >
>> > Do some sorts of chipselects come into play here ? Ie. you can have one
>> > master
>> > with multiple NAND chips connected to it.
>>
>> Most NAND controllers support interacting with several chips (or
>> dies in case your chip embeds several NAND dies), but I
On Wednesday, October 28, 2015 at 05:32:15 PM, Boris Brezillon wrote:
> Hi Marek,
Hi Boris,
> On Wed, 28 Oct 2015 17:11:14 +0100
>
> Marek Vasut wrote:
> > On Wednesday, October 28, 2015 at 08:58:13 AM, Boris Brezillon wrote:
> > > Hi Brian,
> >
> > Hi,
> >
> > [...]
> >
> > > > Are
> > > >
On Wed, Oct 28, 2015 at 05:32:15PM +0100, Boris Brezillon wrote:
> On Wed, 28 Oct 2015 17:11:14 +0100
> Marek Vasut wrote:
> > On Wednesday, October 28, 2015 at 08:58:13 AM, Boris Brezillon wrote:
> > > Hi Brian,
> >
> > Hi,
> >
> > [...]
> >
> > > > Are
> > > > there ever cases we want more
Hi Marek,
On Wed, 28 Oct 2015 17:11:14 +0100
Marek Vasut wrote:
> On Wednesday, October 28, 2015 at 08:58:13 AM, Boris Brezillon wrote:
> > Hi Brian,
>
> Hi,
>
> [...]
>
> > > Are
> > > there ever cases we want more than one (master) MTD per nand_chip? Or
> > > vice versa?
> >
> > Nope, I'd
On Wednesday, October 28, 2015 at 08:58:13 AM, Boris Brezillon wrote:
> Hi Brian,
Hi,
[...]
> > Are
> > there ever cases we want more than one (master) MTD per nand_chip? Or
> > vice versa?
>
> Nope, I'd say that you always have a 1:1 relationship between a master
> MTD device and a NAND
Hi Brian,
On Tue, 27 Oct 2015 18:01:02 -0700
Brian Norris wrote:
> On Tue, Oct 27, 2015 at 10:54:46AM -0700, Brian Norris wrote:
> > On Tue, Oct 27, 2015 at 08:42:00AM +0100, Boris Brezillon wrote:
> > > On Mon, 26 Oct 2015 19:31:06 -0700
> > > I like the idea, but how about pushing the
Hi Brian,
On Tue, 27 Oct 2015 10:54:46 -0700
Brian Norris wrote:
> Hi Boris,
>
> On Tue, Oct 27, 2015 at 08:42:00AM +0100, Boris Brezillon wrote:
> > On Mon, 26 Oct 2015 19:31:06 -0700
> > Brian Norris wrote:
> >
> > > It seems more logical to use a device node directly associated with the
>
Hi Brian,
On Tue, 27 Oct 2015 18:01:02 -0700
Brian Norris wrote:
> On Tue, Oct 27, 2015 at 10:54:46AM -0700, Brian Norris wrote:
> > On Tue, Oct 27, 2015 at 08:42:00AM +0100, Boris Brezillon wrote:
> > > On Mon, 26 Oct 2015 19:31:06 -0700
> > > I like the idea, but
Hi Brian,
On Tue, 27 Oct 2015 10:54:46 -0700
Brian Norris wrote:
> Hi Boris,
>
> On Tue, Oct 27, 2015 at 08:42:00AM +0100, Boris Brezillon wrote:
> > On Mon, 26 Oct 2015 19:31:06 -0700
> > Brian Norris wrote:
> >
> > > It seems more
Hi Marek,
On Wed, 28 Oct 2015 17:11:14 +0100
Marek Vasut wrote:
> On Wednesday, October 28, 2015 at 08:58:13 AM, Boris Brezillon wrote:
> > Hi Brian,
>
> Hi,
>
> [...]
>
> > > Are
> > > there ever cases we want more than one (master) MTD per nand_chip? Or
> > > vice versa?
> >
On Wednesday, October 28, 2015 at 08:58:13 AM, Boris Brezillon wrote:
> Hi Brian,
Hi,
[...]
> > Are
> > there ever cases we want more than one (master) MTD per nand_chip? Or
> > vice versa?
>
> Nope, I'd say that you always have a 1:1 relationship between a master
> MTD device and a NAND
On Wed, Oct 28, 2015 at 05:32:15PM +0100, Boris Brezillon wrote:
> On Wed, 28 Oct 2015 17:11:14 +0100
> Marek Vasut wrote:
> > On Wednesday, October 28, 2015 at 08:58:13 AM, Boris Brezillon wrote:
> > > Hi Brian,
> >
> > Hi,
> >
> > [...]
> >
> > > > Are
> > > > there ever cases
Brian Norris writes:
>> >
>> > Do some sorts of chipselects come into play here ? Ie. you can have one
>> > master
>> > with multiple NAND chips connected to it.
>>
>> Most NAND controllers support interacting with several chips (or
>> dies in case your chip
On Wednesday, October 28, 2015 at 05:32:15 PM, Boris Brezillon wrote:
> Hi Marek,
Hi Boris,
> On Wed, 28 Oct 2015 17:11:14 +0100
>
> Marek Vasut wrote:
> > On Wednesday, October 28, 2015 at 08:58:13 AM, Boris Brezillon wrote:
> > > Hi Brian,
> >
> > Hi,
> >
> > [...]
> >
> >
On Wednesday, October 28, 2015 at 09:55:24 PM, Robert Jarzmik wrote:
> Brian Norris writes:
> >> > Do some sorts of chipselects come into play here ? Ie. you can have
> >> > one master with multiple NAND chips connected to it.
> >>
> >> Most NAND controllers support
On Tue, Oct 27, 2015 at 10:54:46AM -0700, Brian Norris wrote:
> On Tue, Oct 27, 2015 at 08:42:00AM +0100, Boris Brezillon wrote:
> > On Mon, 26 Oct 2015 19:31:06 -0700
> > I like the idea, but how about pushing the solution even further and
> > killing the ->flash_node field which AFAICT is
Hi Boris,
On Tue, Oct 27, 2015 at 08:42:00AM +0100, Boris Brezillon wrote:
> On Mon, 26 Oct 2015 19:31:06 -0700
> Brian Norris wrote:
>
> > It seems more logical to use a device node directly associated with the
> > MTD master device (i.e., mtd->dev.of_node field) rather than requiring
> >
Hi Brian,
On Mon, 26 Oct 2015 19:31:06 -0700
Brian Norris wrote:
> It seems more logical to use a device node directly associated with the
> MTD master device (i.e., mtd->dev.of_node field) rather than requiring
> auxiliary partition parser information to be passed in by the driver in
> a
Hi Brian,
On Mon, 26 Oct 2015 19:31:06 -0700
Brian Norris wrote:
> It seems more logical to use a device node directly associated with the
> MTD master device (i.e., mtd->dev.of_node field) rather than requiring
> auxiliary partition parser information to be passed
Hi Boris,
On Tue, Oct 27, 2015 at 08:42:00AM +0100, Boris Brezillon wrote:
> On Mon, 26 Oct 2015 19:31:06 -0700
> Brian Norris wrote:
>
> > It seems more logical to use a device node directly associated with the
> > MTD master device (i.e., mtd->dev.of_node field)
On Tue, Oct 27, 2015 at 10:54:46AM -0700, Brian Norris wrote:
> On Tue, Oct 27, 2015 at 08:42:00AM +0100, Boris Brezillon wrote:
> > On Mon, 26 Oct 2015 19:31:06 -0700
> > I like the idea, but how about pushing the solution even further and
> > killing the ->flash_node field which AFAICT is
It seems more logical to use a device node directly associated with the
MTD master device (i.e., mtd->dev.of_node field) rather than requiring
auxiliary partition parser information to be passed in by the driver in
a separate struct.
This patch supports the mtd->dev.of_node field, deprecates the
It seems more logical to use a device node directly associated with the
MTD master device (i.e., mtd->dev.of_node field) rather than requiring
auxiliary partition parser information to be passed in by the driver in
a separate struct.
This patch supports the mtd->dev.of_node field, deprecates the
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