From: Boqun Feng Sent: Monday, February 22, 2021 10:47 PM
>
> On Wed, Jan 27, 2021 at 12:23:45PM -0800, Michael Kelley wrote:
> > STIMER0 interrupts are most naturally modeled as per-cpu IRQs. But
> > because x86/x64 doesn't have per-cpu IRQs, the core STIMER0 interrupt
> > handling machinery is
On Wed, Jan 27, 2021 at 12:23:45PM -0800, Michael Kelley wrote:
> STIMER0 interrupts are most naturally modeled as per-cpu IRQs. But
> because x86/x64 doesn't have per-cpu IRQs, the core STIMER0 interrupt
> handling machinery is done in code under arch/x86 and Linux IRQs are
> not used. Adding
From: Wei Liu Sent: Monday, February 1, 2021 11:53 AM
>
> On Wed, Jan 27, 2021 at 12:23:45PM -0800, Michael Kelley wrote:
> [...]
> > +static int hv_setup_stimer0_irq(void)
> > +{
> > + int ret;
> > +
> > + ret = acpi_register_gsi(NULL, HYPERV_STIMER0_VECTOR,
> > +
On Wed, Jan 27, 2021 at 12:23:45PM -0800, Michael Kelley wrote:
[...]
> +static int hv_setup_stimer0_irq(void)
> +{
> + int ret;
> +
> + ret = acpi_register_gsi(NULL, HYPERV_STIMER0_VECTOR,
> + ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_HIGH);
When IO-APIC is enabled on x86,
STIMER0 interrupts are most naturally modeled as per-cpu IRQs. But
because x86/x64 doesn't have per-cpu IRQs, the core STIMER0 interrupt
handling machinery is done in code under arch/x86 and Linux IRQs are
not used. Adding support for ARM64 means adding equivalent code
using per-cpu IRQs under
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