Re: [PATCH 10/17] RISC-V: Atomic and Locking Code

On Wed, 12 Jul 2017 05:40:49 PDT (-0700), boqun.f...@gmail.com wrote: > On Tue, Jul 11, 2017 at 06:31:23PM -0700, Palmer Dabbelt wrote: > [...] >> diff --git a/arch/riscv/include/asm/bitops.h >> b/arch/riscv/include/asm/bitops.h >> new file mode 100644 >> index ..b0a0c76e966a >> ---

Re: [PATCH 10/17] RISC-V: Atomic and Locking Code

On Wed, 12 Jul 2017 05:40:49 PDT (-0700), boqun.f...@gmail.com wrote: > On Tue, Jul 11, 2017 at 06:31:23PM -0700, Palmer Dabbelt wrote: > [...] >> diff --git a/arch/riscv/include/asm/bitops.h >> b/arch/riscv/include/asm/bitops.h >> new file mode 100644 >> index ..b0a0c76e966a >> ---

Re: [PATCH 10/17] RISC-V: Atomic and Locking Code

On Wed, Jul 12, 2017 at 3:31 AM, Palmer Dabbelt wrote: > +/* > + * FIXME: I'm flip-flopping on whether or not we should keep this or enforce > + * the ordering with I/O on spinlocks. The worry is that drivers won't get > + * this correct, but I also don't want to introduce a

Re: [PATCH 10/17] RISC-V: Atomic and Locking Code

On Wed, Jul 12, 2017 at 3:31 AM, Palmer Dabbelt wrote: > +/* > + * FIXME: I'm flip-flopping on whether or not we should keep this or enforce > + * the ordering with I/O on spinlocks. The worry is that drivers won't get > + * this correct, but I also don't want to introduce a fence into the lock

Re: [PATCH 10/17] RISC-V: Atomic and Locking Code

On Wed, Jul 12, 2017 at 08:40:49PM +0800, Boqun Feng wrote: > > +/** > > + * set_bit - Atomically set a bit in memory > > + * @nr: the bit to set > > + * @addr: the address to start counting from > > + * > > + * This function is atomic and may not be reordered. See __set_bit() > > This is

Re: [PATCH 10/17] RISC-V: Atomic and Locking Code

On Wed, Jul 12, 2017 at 08:40:49PM +0800, Boqun Feng wrote: > > +/** > > + * set_bit - Atomically set a bit in memory > > + * @nr: the bit to set > > + * @addr: the address to start counting from > > + * > > + * This function is atomic and may not be reordered. See __set_bit() > > This is

Re: [PATCH 10/17] RISC-V: Atomic and Locking Code

On Wed, Jul 12, 2017 at 08:40:49PM +0800, Boqun Feng wrote: [...] > > +/** > > + * set_bit - Atomically set a bit in memory > > + * @nr: the bit to set > > + * @addr: the address to start counting from > > + * > > + * This function is atomic and may not be reordered. See __set_bit() > > This is

Re: [PATCH 10/17] RISC-V: Atomic and Locking Code

On Wed, Jul 12, 2017 at 08:40:49PM +0800, Boqun Feng wrote: [...] > > +/** > > + * set_bit - Atomically set a bit in memory > > + * @nr: the bit to set > > + * @addr: the address to start counting from > > + * > > + * This function is atomic and may not be reordered. See __set_bit() > > This is

Re: [PATCH 10/17] RISC-V: Atomic and Locking Code

On Tue, Jul 11, 2017 at 06:31:23PM -0700, Palmer Dabbelt wrote: [...] > diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h > new file mode 100644 > index ..b0a0c76e966a > --- /dev/null > +++ b/arch/riscv/include/asm/bitops.h > @@ -0,0 +1,216 @@ > +/* > + *

Re: [PATCH 10/17] RISC-V: Atomic and Locking Code

On Tue, Jul 11, 2017 at 06:31:23PM -0700, Palmer Dabbelt wrote: [...] > diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h > new file mode 100644 > index ..b0a0c76e966a > --- /dev/null > +++ b/arch/riscv/include/asm/bitops.h > @@ -0,0 +1,216 @@ > +/* > + *

[PATCH 10/17] RISC-V: Atomic and Locking Code

This contains all the code that directly interfaces with the RISC-V memory model. While this code corforms to the current RISC-V ISA specifications (user 2.2 and priv 1.10), the memory model is somewhat underspecified in those documents. There is a working group that hopes to produce a formal

[PATCH 10/17] RISC-V: Atomic and Locking Code

This contains all the code that directly interfaces with the RISC-V memory model. While this code corforms to the current RISC-V ISA specifications (user 2.2 and priv 1.10), the memory model is somewhat underspecified in those documents. There is a working group that hopes to produce a formal

[PATCH 10/17] RISC-V: Atomic and Locking Code

This contains all the code that directly interfaces with the RISC-V memory model. While this code corforms to the current RISC-V ISA specifications (user 2.2 and priv 1.10), the memory model is somewhat underspecified in those documents. There is a working group that hopes to produce a formal

[PATCH 10/17] RISC-V: Atomic and Locking Code

This contains all the code that directly interfaces with the RISC-V memory model. While this code corforms to the current RISC-V ISA specifications (user 2.2 and priv 1.10), the memory model is somewhat underspecified in those documents. There is a working group that hopes to produce a formal