Hi Vineet,
On Thu, 2016-04-28 at 19:26 +0530, Vineet Gupta wrote:
> On Thursday 28 April 2016 07:16 PM, Alexey Brodkin wrote:
> >
> > >
> > > >
> > > > Note that the IOC start alignment needs to follow
> > > > max(4k, size). What will be maximum size of frame buffer - 16M always !
> > What do
Hi Vineet,
On Thu, 2016-04-28 at 19:26 +0530, Vineet Gupta wrote:
> On Thursday 28 April 2016 07:16 PM, Alexey Brodkin wrote:
> >
> > >
> > > >
> > > > Note that the IOC start alignment needs to follow
> > > > max(4k, size). What will be maximum size of frame buffer - 16M always !
> > What do
On Thursday 28 April 2016 07:16 PM, Alexey Brodkin wrote:
>> > Note that the IOC start alignment needs to follow
>> > max(4k, size). What will be maximum size of frame buffer - 16M always !
> What do you mean by that?
For HS38, we intend to bypass the frame buffer traffic from IOC port. So the
On Thursday 28 April 2016 07:16 PM, Alexey Brodkin wrote:
>> > Note that the IOC start alignment needs to follow
>> > max(4k, size). What will be maximum size of frame buffer - 16M always !
> What do you mean by that?
For HS38, we intend to bypass the frame buffer traffic from IOC port. So the
Hi Vineet,
On Thu, 2016-04-28 at 09:56 +0530, Vineet Gupta wrote:
[snip]
> >
> > diff --git a/arch/arc/boot/dts/axc001.dtsi b/arch/arc/boot/dts/axc001.dtsi
> > index 420dcfd..ae6162d 100644
> > --- a/arch/arc/boot/dts/axc001.dtsi
> > +++ b/arch/arc/boot/dts/axc001.dtsi
> > @@ -95,6 +95,24 @@
>
Hi Vineet,
On Thu, 2016-04-28 at 09:56 +0530, Vineet Gupta wrote:
[snip]
> >
> > diff --git a/arch/arc/boot/dts/axc001.dtsi b/arch/arc/boot/dts/axc001.dtsi
> > index 420dcfd..ae6162d 100644
> > --- a/arch/arc/boot/dts/axc001.dtsi
> > +++ b/arch/arc/boot/dts/axc001.dtsi
> > @@ -95,6 +95,24 @@
>
On Wednesday 27 April 2016 08:05 PM, Alexey Brodkin wrote:
> Allocation of a frame buffer memory in a special memory region
> allows bypassing of so-called IO Coherency aperture
> which is typically set as a range 0x8z-0xAz.
>
> I.e. all data traffic to PGU bypasses IO Coherency block
> and saves
On Wednesday 27 April 2016 08:05 PM, Alexey Brodkin wrote:
> Allocation of a frame buffer memory in a special memory region
> allows bypassing of so-called IO Coherency aperture
> which is typically set as a range 0x8z-0xAz.
>
> I.e. all data traffic to PGU bypasses IO Coherency block
> and saves
Allocation of a frame buffer memory in a special memory region
allows bypassing of so-called IO Coherency aperture
which is typically set as a range 0x8z-0xAz.
I.e. all data traffic to PGU bypasses IO Coherency block
and saves its bandwidth for other peripherals.
Even though for AXS101 (which
Allocation of a frame buffer memory in a special memory region
allows bypassing of so-called IO Coherency aperture
which is typically set as a range 0x8z-0xAz.
I.e. all data traffic to PGU bypasses IO Coherency block
and saves its bandwidth for other peripherals.
Even though for AXS101 (which
10 matches
Mail list logo
