Hi Suravee,
On 27/06/14 16:43, Suravee Suthikulpanit wrote:
> Hi Marc,
>
> After looking at the GICv3 implementation and trying to understand how
> you architect the driver, I have a couple questions below.
>
> > On 06/24/2014 04:52 AM, Marc Zyngier wrote:
>> Hi Suravee,
>>
>> On 24/06/14
Hi Marc,
After looking at the GICv3 implementation and trying to understand how
you architect the driver, I have a couple questions below.
> On 06/24/2014 04:52 AM, Marc Zyngier wrote:
Hi Suravee,
On 24/06/14 01:33, suravee.suthikulpa...@amd.com wrote:
+ pr_info("GICv2m: SPI range
Hi Marc,
After looking at the GICv3 implementation and trying to understand how
you architect the driver, I have a couple questions below.
On 06/24/2014 04:52 AM, Marc Zyngier wrote:
Hi Suravee,
On 24/06/14 01:33, suravee.suthikulpa...@amd.com wrote:
+ pr_info(GICv2m: SPI range
Hi Suravee,
On 27/06/14 16:43, Suravee Suthikulpanit wrote:
Hi Marc,
After looking at the GICv3 implementation and trying to understand how
you architect the driver, I have a couple questions below.
On 06/24/2014 04:52 AM, Marc Zyngier wrote:
Hi Suravee,
On 24/06/14 01:33,
On Wed, Jun 25, 2014 at 03:55:54AM +0100, Suravee Suthikulanit wrote:
> Mark,
>
> Thank you for all your comments. Please see my reply below. I have
> omitted the minor ones.
Likewise.
> >> +static void free_msi_irq(struct gicv2m_msi_data *data, unsigned int irq)
> >> +{
> >> + int pos;
On Wed, Jun 25, 2014 at 03:55:54AM +0100, Suravee Suthikulanit wrote:
Mark,
Thank you for all your comments. Please see my reply below. I have
omitted the minor ones.
Likewise.
+static void free_msi_irq(struct gicv2m_msi_data *data, unsigned int irq)
+{
+ int pos;
+
+
On 6/24/2014 4:52 AM, Marc Zyngier wrote:
Overall, this requires to be re-architected. If you want to have a look
at the way I did the GICv3 ITS support:
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
gicv3/its
Thanks,
Thanks for the review comments. I'll take a look at
Mark,
Thank you for all your comments. Please see my reply below. I have
omitted the minor ones.
On 6/24/2014 5:11 AM, Mark Rutland wrote:
On Tue, Jun 24, 2014 at 01:33:00AM +0100, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit
+static int alloc_msi_irq(struct
On Tue, Jun 24, 2014 at 01:33:00AM +0100, suravee.suthikulpa...@amd.com wrote:
> From: Suravee Suthikulpanit
>
> GICv2m extends GICv2 to support MSI(-X) with a new set of register frames.
>
> This patch introduces support for the non-secure GICv2m register frame.
> This is optional. It uses the
Hi Suravee,
On 24/06/14 01:33, suravee.suthikulpa...@amd.com wrote:
> From: Suravee Suthikulpanit
>
> GICv2m extends GICv2 to support MSI(-X) with a new set of register frames.
>
> This patch introduces support for the non-secure GICv2m register frame.
> This is optional. It uses the
Hi Suravee,
On 24/06/14 01:33, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
GICv2m extends GICv2 to support MSI(-X) with a new set of register frames.
This patch introduces support for the non-secure GICv2m register frame.
This is
On Tue, Jun 24, 2014 at 01:33:00AM +0100, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
GICv2m extends GICv2 to support MSI(-X) with a new set of register frames.
This patch introduces support for the non-secure GICv2m register frame.
This
Mark,
Thank you for all your comments. Please see my reply below. I have
omitted the minor ones.
On 6/24/2014 5:11 AM, Mark Rutland wrote:
On Tue, Jun 24, 2014 at 01:33:00AM +0100, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
+static int
On 6/24/2014 4:52 AM, Marc Zyngier wrote:
Overall, this requires to be re-architected. If you want to have a look
at the way I did the GICv3 ITS support:
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
gicv3/its
Thanks,
Thanks for the review comments. I'll take a look at
From: Suravee Suthikulpanit
GICv2m extends GICv2 to support MSI(-X) with a new set of register frames.
This patch introduces support for the non-secure GICv2m register frame.
This is optional. It uses the "msi-controller" keyword in ARM GIC
devicetree binding to indentify GIC driver that it
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
GICv2m extends GICv2 to support MSI(-X) with a new set of register frames.
This patch introduces support for the non-secure GICv2m register frame.
This is optional. It uses the msi-controller keyword in ARM GIC
devicetree binding to
16 matches
Mail list logo