On Tue, May 20 2014 at 2:26:33 am BST, Feng Kan wrote:
>>> #ifdef CONFIG_CPU_PM
>>> @@ -613,7 +636,7 @@ static void gic_cpu_restore(unsigned int gic_nr)
>>> dist_base + GIC_DIST_PRI + i * 4);
>>>
>>> writel_relaxed(GIC_INT_PRI_THRESHOLD, cpu_base +
On Tue, May 20 2014 at 2:26:33 am BST, Feng Kan f...@apm.com wrote:
#ifdef CONFIG_CPU_PM
@@ -613,7 +636,7 @@ static void gic_cpu_restore(unsigned int gic_nr)
dist_base + GIC_DIST_PRI + i * 4);
writel_relaxed(GIC_INT_PRI_THRESHOLD, cpu_base +
>> #ifdef CONFIG_CPU_PM
>> @@ -613,7 +636,7 @@ static void gic_cpu_restore(unsigned int gic_nr)
>> dist_base + GIC_DIST_PRI + i * 4);
>>
>> writel_relaxed(GIC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
>> - writel_relaxed(GIC_CPU_ENABLE,
On Fri, May 16 2014 at 11:20:13 pm BST, Feng Kan wrote:
> This change is made to preserve the GIC v2 bypass bits in the
> GIC_CPU_CTRL register (also known as the GICC_CTLR register in spec).
> This code will preserve all bits configured by the bootloader regarding
> v2 bypass group bits. In the
#ifdef CONFIG_CPU_PM
@@ -613,7 +636,7 @@ static void gic_cpu_restore(unsigned int gic_nr)
dist_base + GIC_DIST_PRI + i * 4);
writel_relaxed(GIC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
- writel_relaxed(GIC_CPU_ENABLE, cpu_base +
On Fri, May 16 2014 at 11:20:13 pm BST, Feng Kan f...@apm.com wrote:
This change is made to preserve the GIC v2 bypass bits in the
GIC_CPU_CTRL register (also known as the GICC_CTLR register in spec).
This code will preserve all bits configured by the bootloader regarding
v2 bypass group bits.
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