On Fri, 24 May 2019 06:48:47 PDT (-0700), and...@lunn.ch wrote:
On Fri, May 24, 2019 at 10:22:06AM +0530, Yash Shah wrote:
On Thu, May 23, 2019 at 8:24 PM Andrew Lunn wrote:
>
> > +static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
> > +
On Fri, May 24, 2019 at 10:22:06AM +0530, Yash Shah wrote:
> On Thu, May 23, 2019 at 8:24 PM Andrew Lunn wrote:
> >
> > > +static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
> > > + unsigned long parent_rate)
> > > +{
> > > + rate =
On Thu, May 23, 2019 at 8:24 PM Andrew Lunn wrote:
>
> > +static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
> > + unsigned long parent_rate)
> > +{
> > + rate = fu540_macb_tx_round_rate(hw, rate, _rate);
> > + iowrite32(rate !=
> +static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + rate = fu540_macb_tx_round_rate(hw, rate, _rate);
> + iowrite32(rate != 12500, mgmt->reg);
That looks odd. Writing the result of a
The management IP block is tightly coupled with the Cadence MACB IP
block on the FU540, and manages many of the boundary signals from the
MACB IP. This patch only controls the tx_clk input signal to the MACB
IP. Future patches may add support for monitoring or controlling other
IP boundary
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