On 04.12.2020 17:38, Florian Fainelli wrote:
On 12/4/2020 1:37 AM, Rafał Miłecki wrote:
From: Rafał Miłecki
This controller is responsible for OHCI, EHCI, XHCI and PHYs setup that
has to be handled in the proper order.
One unusual thing about this controller is that is provides access to
the
On 12/4/2020 1:37 AM, Rafał Miłecki wrote:
> From: Rafał Miłecki
>
> This controller is responsible for OHCI, EHCI, XHCI and PHYs setup that
> has to be handled in the proper order.
>
> One unusual thing about this controller is that is provides access to
> the MDIO bus. There are two
On Fri, 4 Dec 2020 at 17:13, Philipp Zabel wrote:
> On Fri, 2020-12-04 at 10:37 +0100, Rafał Miłecki wrote:
> > From: Rafał Miłecki
> >
> > This controller is responsible for OHCI, EHCI, XHCI and PHYs setup that
> > has to be handled in the proper order.
> >
> > One unusual thing about this
Hi Rafał,
On Fri, 2020-12-04 at 10:37 +0100, Rafał Miłecki wrote:
> From: Rafał Miłecki
>
> This controller is responsible for OHCI, EHCI, XHCI and PHYs setup that
> has to be handled in the proper order.
>
> One unusual thing about this controller is that is provides access to
> the MDIO bus.
From: Rafał Miłecki
This controller is responsible for OHCI, EHCI, XHCI and PHYs setup that
has to be handled in the proper order.
One unusual thing about this controller is that is provides access to
the MDIO bus. There are two registers (in the middle of block space)
responsible for that. For
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