From: James Liao
This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.
Signed-off-by: James Liao
Signed-off-by: Henry Chen
Signed-off-by: Sascha Hauer
---
drivers/clk/Makefile| 1 +
drivers/clk/mediatek/Makefile | 1 +
From: James Liao jamesjj.l...@mediatek.com
This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
Signed-off-by: Henry Chen henryc.c...@mediatek.com
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
2015-03-31 20:16 GMT+02:00 Sascha Hauer :
> From: James Liao
>
> This patch adds common clock support for Mediatek SoCs, including plls,
> muxes and clock gates.
>
> Signed-off-by: James Liao
> Signed-off-by: Henry Chen
> Signed-off-by: Sascha Hauer
> ---
> drivers/clk/Makefile|
2015-03-31 20:16 GMT+02:00 Sascha Hauer s.ha...@pengutronix.de:
From: James Liao jamesjj.l...@mediatek.com
This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
Signed-off-by: Henry Chen
From: James Liao
This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.
Signed-off-by: James Liao
Signed-off-by: Henry Chen
Signed-off-by: Sascha Hauer
---
drivers/clk/Makefile| 1 +
drivers/clk/mediatek/Makefile | 1 +
From: James Liao jamesjj.l...@mediatek.com
This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
Signed-off-by: Henry Chen henryc.c...@mediatek.com
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
Quoting Sascha Hauer (2015-03-30 10:40:41)
> +static void mtk_pll_set_rate_regs(struct clk_hw *hw, u32 pcw,
> + int postdiv)
> +{
> + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
> + u32 con1, pd, val;
> + int pll_en;
> +
> + /* set postdiv */
> + pd =
On Mon, Mar 30, 2015 at 10:55:46AM -0700, Joe Perches wrote:
> On Mon, 2015-03-30 at 19:40 +0200, Sascha Hauer wrote:
> > This patch adds common clock support for Mediatek SoCs, including plls,
> > muxes and clock gates.
>
> trivia:
>
> > diff --git a/drivers/clk/mediatek/clk-gate.c
> >
On Mon, 2015-03-30 at 19:40 +0200, Sascha Hauer wrote:
> This patch adds common clock support for Mediatek SoCs, including plls,
> muxes and clock gates.
trivia:
> diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
> +static int mtk_cg_bit_is_cleared(struct clk_hw
From: James Liao
This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.
Signed-off-by: James Liao
Signed-off-by: Henry Chen
Signed-off-by: Sascha Hauer
---
drivers/clk/Makefile| 1 +
drivers/clk/mediatek/Makefile | 1 +
From: James Liao jamesjj.l...@mediatek.com
This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
Signed-off-by: Henry Chen henryc.c...@mediatek.com
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
On Mon, 2015-03-30 at 19:40 +0200, Sascha Hauer wrote:
This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.
trivia:
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
+static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
On Mon, Mar 30, 2015 at 10:55:46AM -0700, Joe Perches wrote:
On Mon, 2015-03-30 at 19:40 +0200, Sascha Hauer wrote:
This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.
trivia:
diff --git a/drivers/clk/mediatek/clk-gate.c
Quoting Sascha Hauer (2015-03-30 10:40:41)
+static void mtk_pll_set_rate_regs(struct clk_hw *hw, u32 pcw,
+ int postdiv)
+{
+ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
+ u32 con1, pd, val;
+ int pll_en;
+
+ /* set postdiv */
+ pd =
From: James Liao
This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.
Signed-off-by: James Liao
Signed-off-by: Henry Chen
Signed-off-by: Sascha Hauer
---
drivers/clk/Makefile| 1 +
drivers/clk/mediatek/Makefile | 1 +
From: James Liao jamesjj.l...@mediatek.com
This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
Signed-off-by: Henry Chen henryc.c...@mediatek.com
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
From: James Liao
This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.
Signed-off-by: James Liao
Signed-off-by: Henry Chen
Signed-off-by: Sascha Hauer
---
drivers/clk/Makefile| 1 +
drivers/clk/mediatek/Makefile | 1 +
From: James Liao jamesjj.l...@mediatek.com
This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
Signed-off-by: Henry Chen henryc.c...@mediatek.com
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
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