Re: [PATCH 3/3] irqchip/GICv2m: Fix GICv2m build warning on 32 bits

On Thu, 24 Sep 2015 11:19:33 +0300 Pavel Fedin wrote: > Hello! > > > From: Pavel Fedin > > > > After GICv2m was enabled for 32-bit ARM kernel, a warning popped up: > > Thank you for the cooperation, i'm now back from my vacation. > What about the first patch in the series, which actually

RE: [PATCH 3/3] irqchip/GICv2m: Fix GICv2m build warning on 32 bits

Hello! > From: Pavel Fedin > > After GICv2m was enabled for 32-bit ARM kernel, a warning popped up: Thank you for the cooperation, i'm now back from my vacation. What about the first patch in the series, which actually enables GICv2m on 32 bits? I don't see it anywhere, neither there are

RE: [PATCH 3/3] irqchip/GICv2m: Fix GICv2m build warning on 32 bits

Hello! > From: Pavel Fedin > > After GICv2m was enabled for 32-bit ARM kernel, a warning popped up: Thank you for the cooperation, i'm now back from my vacation. What about the first patch in the series, which actually enables GICv2m on 32 bits? I don't see it

Re: [PATCH 3/3] irqchip/GICv2m: Fix GICv2m build warning on 32 bits

On Thu, 24 Sep 2015 11:19:33 +0300 Pavel Fedin wrote: > Hello! > > > From: Pavel Fedin > > > > After GICv2m was enabled for 32-bit ARM kernel, a warning popped up: > > Thank you for the cooperation, i'm now back from my vacation. > What about the

[PATCH 3/3] irqchip/GICv2m: Fix GICv2m build warning on 32 bits

From: Pavel Fedin After GICv2m was enabled for 32-bit ARM kernel, a warning popped up: drivers/irqchip/irq-gic-v2m.c: In function ‘gicv2m_compose_msi_msg’: drivers/irqchip/irq-gic-v2m.c:100:2: warning: right shift count >= width of type [enabled by default] msg->address_hi = (u32) (addr >>

[PATCH 3/3] irqchip/GICv2m: Fix GICv2m build warning on 32 bits

From: Pavel Fedin After GICv2m was enabled for 32-bit ARM kernel, a warning popped up: drivers/irqchip/irq-gic-v2m.c: In function ‘gicv2m_compose_msi_msg’: drivers/irqchip/irq-gic-v2m.c:100:2: warning: right shift count >= width of type [enabled by default]