Hi Boris,
On 03/04/2016 04:38 AM, Borislav Petkov wrote:
On Tue, Mar 01, 2016 at 10:38:19AM -0600, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Addition of the Arria10 L2 Cache ECC handling. The major
changes affect the L2 ECC registers not being
Hi Boris,
On 03/04/2016 04:38 AM, Borislav Petkov wrote:
On Tue, Mar 01, 2016 at 10:38:19AM -0600, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Addition of the Arria10 L2 Cache ECC handling. The major
changes affect the L2 ECC registers not being grouped
together. The Arria10 IRQ
On Tue, Mar 01, 2016 at 10:38:19AM -0600, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Addition of the Arria10 L2 Cache ECC handling. The major
> changes affect the L2 ECC registers not being grouped
> together. The Arria10 IRQ status needs to be
On Tue, Mar 01, 2016 at 10:38:19AM -0600, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Addition of the Arria10 L2 Cache ECC handling. The major
> changes affect the L2 ECC registers not being grouped
> together. The Arria10 IRQ status needs to be mapped into
> a different region.
From: Thor Thayer
Addition of the Arria10 L2 Cache ECC handling. The major
changes affect the L2 ECC registers not being grouped
together. The Arria10 IRQ status needs to be mapped into
a different region. The mapping occurs in the L2 specific
function.
Important
From: Thor Thayer
Addition of the Arria10 L2 Cache ECC handling. The major
changes affect the L2 ECC registers not being grouped
together. The Arria10 IRQ status needs to be mapped into
a different region. The mapping occurs in the L2 specific
function.
Important changes include:
1) Move private
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