On Fri, 3 Aug 2018, Palmer Dabbelt wrote:
> On Wed, 01 Aug 2018 11:55:06 PDT (-0700), t...@linutronix.de wrote:
> > Is there some high level documentation about the design (or the lack of) or
> > can someone give a concise explanation how this stuff is supposed to work?
> As part of our original pu
On Wed, 01 Aug 2018 11:55:06 PDT (-0700), t...@linutronix.de wrote:
On Wed, 25 Jul 2018, Christoph Hellwig wrote:
On Wed, Jul 25, 2018 at 12:18:39PM +0100, Marc Zyngier wrote:
> This feels odd. It means that you cannot have the following sequence:
>
>local_irq_disable();
>enable_irq(x)
On Thu, 2 Aug 2018, Christoph Hellwig wrote:
> On Thu, Aug 02, 2018 at 11:35:43AM +0200, Thomas Gleixner wrote:
> > So that's the low level per cpu interrupt/exception distribution mechanism,
> > i.e. a distinct per cpu 'vector' space with fixed functionality. It does
> > not make sense to actually
On Thu, Aug 02, 2018 at 11:35:43AM +0200, Thomas Gleixner wrote:
> On Thu, 2 Aug 2018, Christoph Hellwig wrote:
> > The cpu local interrupt handling, which was irq-riscv-intc.c in this
> > series and has been moved to arch/riscv/kernel/irq.c in my new series
> > is split over a few control register
On Thu, 2 Aug 2018, Christoph Hellwig wrote:
> The cpu local interrupt handling, which was irq-riscv-intc.c in this
> series and has been moved to arch/riscv/kernel/irq.c in my new series
> is split over a few control registers (CSRs in RISC-V speak):
>
> The exception handler, which includes the
On Wed, Aug 01, 2018 at 08:55:06PM +0200, Thomas Gleixner wrote:
> Confused. The timer and the IPI are separate causes and have nothing to do
> with the per cpu irq domain. That's what the low level interrupt handling
> code tells me.
Yes.
> If I understand correctly then the per cpu irq domain i
On Wed, 25 Jul 2018, Christoph Hellwig wrote:
> On Wed, Jul 25, 2018 at 12:18:39PM +0100, Marc Zyngier wrote:
> > This feels odd. It means that you cannot have the following sequence:
> >
> > local_irq_disable();
> > enable_irq(x); // where x is owned by a remote hart
> >
> > as smp_ca
On Thu, Jul 26, 2018 at 1:57 PM, Christoph Hellwig wrote:
> On Thu, Jul 26, 2018 at 09:08:00AM +0530, Anup Patel wrote:
>> Actually, RISCV HLIC and PLIC are very similar to RPi2 and RPi3 SOCs.
>>
>> On RPi2 and RPi3, we have per-CPU BCM2836 local intc and the global
>> interrupts are managed using
On Thu, Jul 26, 2018 at 09:08:00AM +0530, Anup Patel wrote:
> Actually, RISCV HLIC and PLIC are very similar to RPi2 and RPi3 SOCs.
>
> On RPi2 and RPi3, we have per-CPU BCM2836 local intc and the global
> interrupts are managed using BCM2835 intc. You should certainly have
> a look a this drivers
On Wed, Jul 25, 2018 at 4:54 PM, Christoph Hellwig wrote:
> On Wed, Jul 25, 2018 at 12:18:39PM +0100, Marc Zyngier wrote:
>> This feels odd. It means that you cannot have the following sequence:
>>
>> local_irq_disable();
>> enable_irq(x); // where x is owned by a remote hart
>>
>> as
On 7/25/18 4:37 AM, Marc Zyngier wrote:
On 25/07/18 12:24, Christoph Hellwig wrote:
On Wed, Jul 25, 2018 at 12:18:39PM +0100, Marc Zyngier wrote:
This feels odd. It means that you cannot have the following sequence:
local_irq_disable();
enable_irq(x); // where x is owned by a r
On 25/07/18 12:24, Christoph Hellwig wrote:
> On Wed, Jul 25, 2018 at 12:18:39PM +0100, Marc Zyngier wrote:
>> This feels odd. It means that you cannot have the following sequence:
>>
>> local_irq_disable();
>> enable_irq(x); // where x is owned by a remote hart
>>
>> as smp_call_function
On Wed, Jul 25, 2018 at 12:18:39PM +0100, Marc Zyngier wrote:
> This feels odd. It means that you cannot have the following sequence:
>
> local_irq_disable();
> enable_irq(x); // where x is owned by a remote hart
>
> as smp_call_function_single() requires interrupts to be enabled.
>
On 25/07/18 10:36, Christoph Hellwig wrote:
> From: Palmer Dabbelt
>
> This patch adds a driver that manages the local interrupts on each
> RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual.
> The local interrupt controller manages software interrupts, timer
> interrupts, and ha
From: Palmer Dabbelt
This patch adds a driver that manages the local interrupts on each
RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual.
The local interrupt controller manages software interrupts, timer
interrupts, and hardware interrupts (which are routed via the
platform lev
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