From: Thomas Gleixner
3.12-stable review patch. If anyone has any objections, please let me know.
===
commit 15ebb05248d025534773c9ef64915bd888f04e4b upstream.
The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a62c (SPEAr: Switch to common clock
From: Thomas Gleixner t...@linutronix.de
3.12-stable review patch. If anyone has any objections, please let me know.
===
commit 15ebb05248d025534773c9ef64915bd888f04e4b upstream.
The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a62c (SPEAr:
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