On Fri, Jun 15, 2018 at 11:58:10AM +0100, James Hogan wrote:
> On Thu, Jun 14, 2018 at 04:52:10PM -0700, Paul Burton wrote:
> > +#define __RSEQ_ASM_DEFINE_TABLE(version, flags,start_ip,
> > \
>
> Nit: technically all these \'s are on 81st column...
True... I'll replace
On Fri, Jun 15, 2018 at 11:58:10AM +0100, James Hogan wrote:
> On Thu, Jun 14, 2018 at 04:52:10PM -0700, Paul Burton wrote:
> > +#define __RSEQ_ASM_DEFINE_TABLE(version, flags,start_ip,
> > \
>
> Nit: technically all these \'s are on 81st column...
True... I'll replace
- On Jun 15, 2018, at 6:58 AM, James Hogan jho...@kernel.org wrote:
> On Thu, Jun 14, 2018 at 04:52:10PM -0700, Paul Burton wrote:
>> +#define __RSEQ_ASM_DEFINE_TABLE(version, flags, start_ip,
>> \
>
> Nit: technically all these \'s are on 81st column...
>
>>
- On Jun 15, 2018, at 6:58 AM, James Hogan jho...@kernel.org wrote:
> On Thu, Jun 14, 2018 at 04:52:10PM -0700, Paul Burton wrote:
>> +#define __RSEQ_ASM_DEFINE_TABLE(version, flags, start_ip,
>> \
>
> Nit: technically all these \'s are on 81st column...
>
>>
On Thu, Jun 14, 2018 at 04:52:10PM -0700, Paul Burton wrote:
> +#define __RSEQ_ASM_DEFINE_TABLE(version, flags, start_ip,
> \
Nit: technically all these \'s are on 81st column...
> +#define __RSEQ_ASM_DEFINE_ABORT(table_label, label, teardown,
>
On Thu, Jun 14, 2018 at 04:52:10PM -0700, Paul Burton wrote:
> +#define __RSEQ_ASM_DEFINE_TABLE(version, flags, start_ip,
> \
Nit: technically all these \'s are on 81st column...
> +#define __RSEQ_ASM_DEFINE_ABORT(table_label, label, teardown,
>
Implement support for both MIPS32 & MIPS64 in the rseq selftests, in
order to sanity check the recently enabled rseq syscall.
The tests all pass on a MIPS Boston development board running either a
MIPS32r2 interAptiv CPU & a MIPS64r6 I6500 CPU, both of which were
configured with 2 cores each of
Implement support for both MIPS32 & MIPS64 in the rseq selftests, in
order to sanity check the recently enabled rseq syscall.
The tests all pass on a MIPS Boston development board running either a
MIPS32r2 interAptiv CPU & a MIPS64r6 I6500 CPU, both of which were
configured with 2 cores each of
8 matches
Mail list logo