[PATCH 4/5] clk: rockchip: add the vop_determine_rate for vop dclock

Rk3288 has 5 PLLs(APLL, DPLL, CPLL, GPLL, NPLL), APLL is for CPU clock only and DPLL is for DRAM clock only, and other 3 PLls used for all other peripherals. We have to make a total solution for how to campatible all kinds of clock requirement by on chip peripheral controllers. Some controllers

[PATCH 4/5] clk: rockchip: add the vop_determine_rate for vop dclock

Rk3288 has 5 PLLs(APLL, DPLL, CPLL, GPLL, NPLL), APLL is for CPU clock only and DPLL is for DRAM clock only, and other 3 PLls used for all other peripherals. We have to make a total solution for how to campatible all kinds of clock requirement by on chip peripheral controllers. Some controllers