On Mon, Jun 16, 2014 at 11:49:18PM +0200, Stephen Warren wrote:
> On 06/04/2014 05:32 AM, Mikko Perttunen wrote:
> > This makes the SATA PLL be controlled by hardware instead of software.
> > This is required for working SATA support.
>
> Peter, could you please take patches 4 and 5 through the
On Mon, Jun 16, 2014 at 11:49:18PM +0200, Stephen Warren wrote:
On 06/04/2014 05:32 AM, Mikko Perttunen wrote:
This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.
Peter, could you please take patches 4 and 5 through the clock
On 06/04/2014 05:32 AM, Mikko Perttunen wrote:
> This makes the SATA PLL be controlled by hardware instead of software.
> This is required for working SATA support.
Peter, could you please take patches 4 and 5 through the clock tree. As
far as I can tell, there's no compile-time dependency in the
On 06/04/2014 05:32 AM, Mikko Perttunen wrote:
This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.
Peter, could you please take patches 4 and 5 through the clock tree. As
far as I can tell, there's no compile-time dependency in the
This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-pll.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/tegra/clk-pll.c
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