[PATCH 6/6] GPIO: MIPS: lantiq: fix overflow inside stp-xway driver

2012-07-24 Thread John Crispin
The driver was using a 16 bit field for storing the shadow value of the shift register cascade. This resulted in only the first 2 shift registeres receiving the correct data. The third shift register would always receive 0x00. Fix this by using a 32bit field for the shadow value. Signed-off-by:

[PATCH 6/6] GPIO: MIPS: lantiq: fix overflow inside stp-xway driver

2012-07-24 Thread John Crispin
The driver was using a 16 bit field for storing the shadow value of the shift register cascade. This resulted in only the first 2 shift registeres receiving the correct data. The third shift register would always receive 0x00. Fix this by using a 32bit field for the shadow value. Signed-off-by: