Thanks John,
That's fine & understood, it's the month before that when these sat
quietly - through the release of a kernel which they fix a regression in
no less, and despite my having asked Ralf on IRC about them a couple of
weeks before v4.2 was released.
If they just fell off the radar or
Hi Paul,
--> http://www.linux-mips.org/archives/linux-mips/2015-09/msg00057.html
John
On 10/09/2015 20:03, Paul Burton wrote:
> Ralf: is there a reason you've only applied patch 1 of this series?
>
> v4.2 is broken because these didn't get in (despite being submitted well
> before the
Hi Paul,
--> http://www.linux-mips.org/archives/linux-mips/2015-09/msg00057.html
John
On 10/09/2015 20:03, Paul Burton wrote:
> Ralf: is there a reason you've only applied patch 1 of this series?
>
> v4.2 is broken because these didn't get in (despite being submitted well
> before the
Thanks John,
That's fine & understood, it's the month before that when these sat
quietly - through the release of a kernel which they fix a regression in
no less, and despite my having asked Ralf on IRC about them a couple of
weeks before v4.2 was released.
If they just fell off the radar or
Ralf: is there a reason you've only applied patch 1 of this series?
v4.2 is broken because these didn't get in (despite being submitted well
before the release), and master is still broken because they still
haven't gotten in. If there's a reason you didn't merge them please let
me know,
Ralf: is there a reason you've only applied patch 1 of this series?
v4.2 is broken because these didn't get in (despite being submitted well
before the release), and master is still broken because they still
haven't gotten in. If there's a reason you didn't merge them please let
me know,
Commit 977e043d5ea1 ("MIPS: kernel: cps-vec: Replace mips32r2 ISA level
with mips64r2") leads to .set mips64r2 directives being present in 32
bit (ie. CONFIG_32BIT=y) kernels. This is incorrect & leads to MIPS64
instructions being emitted by the assembler when expanding
pseudo-instructions. For
Commit 977e043d5ea1 (MIPS: kernel: cps-vec: Replace mips32r2 ISA level
with mips64r2) leads to .set mips64r2 directives being present in 32
bit (ie. CONFIG_32BIT=y) kernels. This is incorrect leads to MIPS64
instructions being emitted by the assembler when expanding
pseudo-instructions. For
8 matches
Mail list logo
